Xilinx UG075 Virtex-4 FPGA Packaging and Pinout Specification ...

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Preface: About This GuideRAdditional Resources- Digital Clock Manager (DCM)- Phase-Matched Clock Dividers (PMCD)- Block RAM and FIFO memory- Configurable Logic Blocks (CLBs)- SelectIO Resources- SelectIO Logic Resources- Advanced SelectIO Logic Resources• XtremeDSP for Virtex-4 FPGAs User GuideThis guide describes the XtremeDSP slice and includes reference designs for usingDSP48 math functions and various FIR filters.• Virtex-4 FPGA Configuration GuideThis all-encompassing configuration guide includes chapters on configurationinterfaces (serial and SelectMAP), bitstream encryption, Boundary-Scan and JTAGconfiguration, reconfiguration techniques, and readback through the SelectMAP andJTAG interfaces.• Virtex-4 PCB Designer’s GuideThis designer’s guide provides information on the design of PCBs for Virtex-4 devices.It considers all aspects of the PCB from the system level down to the minute details.This guide focuses on strategies for making design decisions at the PCB and interfacelevel.• Virtex-4 RocketIO Multi-Gigabit Transceiver User GuideThis guide describes the RocketIO Multi-Gigabit Transceivers available in theVirtex-4 FX family.• Virtex-4 FPGA Embedded Tri-Mode Ethernet MAC User GuideThis guide describes the Tri-Mode Ethernet Media Access Controller available in theVirtex-4 FX family.• PowerPC 405 Processor Block Reference GuideThis guide is updated to include the PowerPC ® 405 processor block available in theVirtex-4 FX family.To search the database of silicon and software questions and answers, or to create atechnical support case in WebCase, visit the following Xilinx website:http://www.xilinx.com/support8 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008
RTypographical ConventionsTypographical ConventionsThe following typographical conventions are used in this document:Convention Meaning or Use ExampleItalic fontReferences to other documentsEmphasis in textSee the Virtex-4 ConfigurationGuide for more information.The address (F) is asserted afterclock event 2.Underlined Text Indicates a link to a web page. http://www.xilinx.com/virtex4Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 9UG075 (v3.3) September 19, 2008
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Page 4: Virtex-4 FPGA Packaging and Pinout
Page 7: RPrefaceAbout This GuideOrganizatio
Page 11 and 12: RChapter 1Packaging OverviewSummary
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Page 15 and 16: RPin DefinitionsTable 1-3: Virtex-4
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Page 19 and 20: RChapter 2Pinout TablesSummaryThis
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RFF668 Package Pinout Diagram (LX25
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RSupport for Compact Thermal Models
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RChapter 6Package MarkingVirtex-4 D
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