Xilinx UG075 Virtex-4 FPGA Packaging and Pinout Specification ...

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Chapter 1: Packaging OverviewRTable 1-3: Virtex-4 FPGA Pin Definitions (Continued)Pin Name Direction DescriptionTMS_0 Input Boundary-Scan Mode SelectTDP_0, TDN_0 N/A Temperature-sensing diode pins (Anode: TDP, Cathode: TDN).Reserved PinsAVDD_SMInputThis pin is reserved and should be connected to 2.5V (sharing the samePCB supply distribution as V CCAUX is acceptable).AVSS_SM Input This pin is reserved for future use and should be connected to GND.VN_SM Input This pin is reserved for future use and should be connected to GND.VP_SM Input This pin is reserved for future use and should be connected to GND.VREFN_SM Input This pin is reserved for future use and should be connected to GND.VREFP_SM Input This pin is reserved for future use and should be connected to GND.AVDD_ADCInputThis pin is reserved and should be connected to 2.5V (sharing the samePCB supply distribution as V CCAUX is acceptable).AVSS_ADC Input This pin is reserved for future use and should be connected to GND.VN_ADC Input This pin is reserved for future use and should be connected to GND.VP_ADC Input This pin is reserved for future use and should be connected to GND.VREFN_ADC Input This pin is reserved for future use and should be connected to GND.VREFP_ADC Input This pin is reserved for future use and should be connected to GND.RSVD N/A Reserved pin - do not connectOther PinsGND Input Ground.V BATT_#InputDecryptor key memory backup supply. If unused, this pin should be tied toV CC or GND.V CCAUX Input Power-supply pins for auxiliary circuitsV CCINT Input Power-supply pins for the internal core logicV CCO_# Input Power-supply pins for the output drivers (per bank)RocketIO Multi-Gigabit Transceiver (MGT) PinsAVCCAUXRXA_#,AVCCAUXRXB_#InputAnalog power supply for receive circuitry of the RocketIO MGT (1.2V).AVCCAUXTX_# Input Analog power supply for transmit circuitry of the RocketIO MGT (1.2V).AVCCAUXMGT_# Input Analog power supply for global bias (2.5V).GNDA_# Input Ground for the analog circuitry of the RocketIO MGT.MGTCLK_# Input Differential reference clock for the RocketIO MGT.16 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008
RPin DefinitionsTable 1-3: Virtex-4 FPGA Pin Definitions (Continued)Pin Name Direction DescriptionRXPPADA_#,RXPPADB_#RXNPADA_#,RXNPADB_#TXPPADA_#,TXPPADB_#TXNPADA_#,TXNPADB_#VTRXA_#,VTRXB_#VTTXA_#,VTTXB_#InputInputOutputOutputInputInputPositive differential receive port of the RocketIO MGT.Negative differential receive port of the RocketIO MGT.Positive differential transmit port of the RocketIO MGT.Negative differential transmit port of the RocketIO MGT.Receive termination supply for the RocketIO MGT (0V - 2.5V).Transmit termination supply for the RocketIO MGT (1.2V - 1.5V).Notes:1. All dedicated pins (JTAG and configuration) are powered by V CC_CONFIG .2. For more information on lower capacitance pins, see the Virtex-4 User Guide (UG070).3. For more information on RocketIO transceiver pins, see the Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide (UG076).Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 17UG075 (v3.3) September 19, 2008
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Page 4: Virtex-4 FPGA Packaging and Pinout
Page 7 and 8: RPrefaceAbout This GuideOrganizatio
Page 9 and 10: RTypographical ConventionsTypograph
Page 11 and 12: RChapter 1Packaging OverviewSummary
Page 13 and 14: RDevice/Package Combinations and Ma
Page 15: RPin DefinitionsTable 1-3: Virtex-4
Page 19 and 20: RChapter 2Pinout TablesSummaryThis
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RChapter 3Pinout DiagramsSummaryThi
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RSF363 Package Pinout Diagram (LX15
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RSF363 Color-Coded SelectIO and Ban
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RFF668 Package Pinout Diagram (LX25
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RChapter 5Thermal SpecificationsSum
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RSupport for Compact Thermal Models
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RChapter 6Package MarkingVirtex-4 D
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