Xilinx UG075 Virtex-4 FPGA Packaging and Pinout Specification ...

RXilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the developmentof designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit theDocumentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise,without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reservesthe right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errorscontained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection withtechnical support or assistance that may be provided to you in connection with the Information.THE DOCUMENTATION IS DISCLOSED TO YOU “AS-IS” WITH NO WARRANTY OF ANY KIND. XILINX MAKES NO OTHERWARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DOCUMENTATION, INCLUDING ANYWARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTYRIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTALDAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OF THE DOCUMENTATION.© 2004-2008 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinxin the United States and other countries. The PowerPC name and logo are registered trademarks of IBM Corp. and used under license. Allother trademarks are the property of their respective owners.Revision HistoryThe following table shows the revision history for this document.VersionRevision08/02/04 1.0 Initial Xilinx release. (Printed Handbook version.)09/03/04 1.1 Added Chapters 2 and 3.10/05/04 1.2 Removed FF1152 package information from Chapters 2 and 3.11/05/04 1.3 Added FF1152 pinout information, and revised TDN, TDP, ADC, and SM pin references.11/30/04 2.0 • Revised four pins affecting only XC4VFX100 devices in the FF1152 package.• Added FF676 pinout information.• Corrected symbol used for pin AN28 in the FF1513 pinout diagram.• Added MGT pin definitions to Table 1-3.12/21/04 2.1 • Changed four VCCO pins to No Connects in Banks 9 and 10, affecting onlyXC4VFX20 devices in the FF672 package.• Added a colorized SelectIO and bank information diagram for each package.• Made minor changes to pin definitions in Table 1-3.01/19/05 2.2 • Corrected pin A9 in the FF1152 package (Table 2-6), affecting only XC4VFX100devices.• Corrected the FF1152 pinout diagrams.02/10/05 2.3 • Removed FF676 package information from the guide.• Made minor changes to pin definitions in Table 1-3.Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com UG075 (v3.3) September 19, 2008