Xilinx UG075 Virtex-4 FPGA Packaging and Pinout Specification ...

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Chapter 2: Pinout TablesRSF363 Flip-Chip Fine-Pitch BGA PackageAs shown in Table 2-1, Virtex-4 XC4VLX15, XC4VLX25, and XC4VFX12 devices areavailable in the SF363 flip-chip fine-pitch BGA package. The “No Connect” column inTable 2-1 shows pins that are not available in LX15 devices.To be assured of having the very latest Virtex-4 FPGA pinout information, visitwww.xilinx.com and check for any updates to this document. ASCII package pinout filesare also available for download from the Xilinx website.Table 2-1: SF363 Package — LX15, LX25, and FX12 DevicesBank Pin Description Pin Number0 HSWAPEN_0 E130 CCLK_0 E110 D_IN_0 E90 PROG_B_0 F120 INIT_B_0 E120 CS_B_0 E80 DONE_0 F110 RDWR_B_0 F90 VBATT_0 T130 M2_0 R110 PWRDWN_B_0 T100 TMS_0 T80 M0_0 R120 TDO_0 R100 TCK_0 T90 M1_0 T120 DOUT_BUSY_0 T110 TDI_0 R90 TDN_0 E100 TDP_0 F10No Connectsin LX15 and FX12 Devices1 IO_L1P_D31_LC_1 F151 IO_L1N_D30_LC_1 E151 IO_L2P_D29_LC_1 E61 IO_L2N_D28_LC_1 F61 IO_L3P_D27_LC_1 D151 IO_L3N_D26_LC_1 E141 IO_L4P_D25_LC_1 E71 IO_L4N_D24_VREF_LC_1 D620 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008
RSF363 Flip-Chip Fine-Pitch BGA PackageTable 2-1: SF363 Package — LX15, LX25, and FX12 Devices (Continued)Bank Pin Description Pin Number1 IO_L5P_D23_LC_1 D131 IO_L5N_D22_LC_1 C131 IO_L6P_D21_LC_1 C81 IO_L6N_D20_LC_1 D81 IO_L7P_D19_LC_1 D121 IO_L7N_D18_LC_1 C121 IO_L8P_D17_CC_LC_1 C91 IO_L8N_D16_CC_LC_1 D9No Connectsin LX15 and FX12 Devices2 IO_L1P_D15_CC_LC_2 V162 IO_L1N_D14_CC_LC_2 V152 IO_L2P_D13_LC_2 V62 IO_L2N_D12_LC_2 V52 IO_L3P_D11_LC_2 T142 IO_L3N_D10_LC_2 U132 IO_L4P_D9_LC_2 U82 IO_L4N_D8_VREF_LC_2 T72 IO_L5P_D7_LC_2 V132 IO_L5N_D6_LC_2 V122 IO_L6P_D5_LC_2 V92 IO_L6N_D4_LC_2 V82 IO_L7P_D3_LC_2 U122 IO_L7N_D2_LC_2 V112 IO_L8P_D1_LC_2 V102 IO_L8N_D0_LC_2 U93 IO_L1P_GC_CC_LC_3 B123 IO_L1N_GC_CC_LC_3 A113 IO_L2P_GC_VRN_LC_3 A103 IO_L2N_GC_VRP_LC_3 B93 IO_L3P_GC_LC_3 C113 IO_L3N_GC_LC_3 B113 IO_L4P_GC_LC_3 B103 IO_L4N_GC_VREF_LC_3 C103 IO_L5P_GC_LC_3 B13Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 21UG075 (v3.3) September 19, 2008
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Page 4: Virtex-4 FPGA Packaging and Pinout
Page 7 and 8: RPrefaceAbout This GuideOrganizatio
Page 9 and 10: RTypographical ConventionsTypograph
Page 11 and 12: RChapter 1Packaging OverviewSummary
Page 13 and 14: RDevice/Package Combinations and Ma
Page 15 and 16: RPin DefinitionsTable 1-3: Virtex-4
Page 17 and 18: RPin DefinitionsTable 1-3: Virtex-4
Page 19: RChapter 2Pinout TablesSummaryThis
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RChapter 3Pinout DiagramsSummaryThi
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RSF363 Package Pinout Diagram (LX15
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RSF363 Color-Coded SelectIO and Ban
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RFF668 Package Pinout Diagram (LX25
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RVirtex-4 FPGA Power Management Str
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RSupport for Compact Thermal Models
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RChapter 6Package MarkingVirtex-4 D
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