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Xilinx UG075 Virtex-4 FPGA Packaging and Pinout Specification ...

Xilinx UG075 Virtex-4 FPGA Packaging and Pinout Specification ...

Xilinx UG075 Virtex-4 FPGA Packaging and Pinout Specification ...

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RFF668 Flip-Chip Fine-Pitch BGA PackageTable 2-2: FF668 Package — LX15, LX25, LX40, LX60, SX25, SX35, <strong>and</strong> FX12Devices (Continued)Bank Pin Description Pin Number5 IO_L10P_5 B245 IO_L10N_5 B235 IO_L11P_5 F185 IO_L11N_5 E185 IO_L12P_5 E215 IO_L12N_VREF_5 D215 IO_L13P_5 A205 IO_L13N_5 A195 IO_L14P_5 D225 IO_L14N_5 C225 IO_L15P_5 A225 IO_L15N_5 A215 IO_L16P_5 D245 IO_L16N_5 C245 IO_L25P_CC_LC_5 D265 IO_L25N_CC_LC_5 D255 IO_L26P_5 H225 IO_L26N_5 H215 IO_L27P_5 E255 IO_L27N_5 E245 IO_L28P_5 G245 IO_L28N_VREF_5 G235 IO_L29P_5 F265 IO_L29N_5 E265 IO_L30P_5 H245 IO_L30N_5 H235 IO_L31P_5 G265 IO_L31N_5 G255 IO_L32P_5 H265 IO_L32N_5 H25No Connects inLX15, SX25, <strong>and</strong> FX12 Devices6 IO_L1P_6 D106 IO_L1N_6 C106 IO_L2P_6 D96 IO_L2N_6 C86 IO_L3P_6 A8<strong>Virtex</strong>-4 <strong>FPGA</strong> <strong>Packaging</strong> <strong>and</strong> <strong>Pinout</strong> <strong>Specification</strong> www.xilinx.com 35<strong>UG075</strong> (v3.3) September 19, 2008

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