Xilinx UG075 Virtex-4 FPGA Packaging and Pinout Specification ...

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Chapter 1: Packaging OverviewRTable 1-2: Virtex-4 FPGA Available I/Os and RocketIO MGT Pins per Device/Package Combination (Continued)Virtex-4DeviceUser I/Os &RocketIO MGT PinsVirtex-4 FPGA PackageSF363 FF668 FF672 FF676 FF1148 FF1152 FF1513 FF1517Available User I/Os - - - - 576 - 768XC4VFX100RocketIO Transceivers - - - - 20 - 20Differential I/O Pairs - - - - 288 - 384Available User I/Os - - - - - - 768XC4VFX140RocketIO Transceivers - - - - - - 24Differential I/O Pairs - - - - - - 384Pin DefinitionsTable 1-3 provides a description of each pin type listed in Virtex-4 FPGA pinout tables. The“_#” suffix appended to some pin descriptions indicates the bank in which that pin resides.Pins that do not have this suffix appended are not associated with any particular bank. Fora description of RocketIO transceiver pins, see the Virtex-4 RocketIO Multi-GigabitTransceiver User Guide (UG076).Table 1-3: Virtex-4 FPGA Pin DefinitionsPin Name Direction DescriptionUser I/O PinsIO_LXXY_#Multi-Function PinsIO_LXXY_ZZZ_#Input/OutputAll user I/O pins are capable of differential signalling and can implementLVDS, LVDSEXT, ULVDS, BLVDS, LVPECL, or LDT pairs. Each user I/Ois labeled “IO_LXXY_#”, where:IO indicates a user I/O pin.LXXY indicates a differential pair, with XX a unique pair in the bankand Y = [P|N] for the positive/negative sides of the differential pair.Multi-function pins are labelled “IO_LXXY_ZZZ_#”, where ZZZrepresents one or more of the functions described below.For a given multi-function pin, ZZZ is one or more of the following:ADCnDnCC (2)GC (2)Input/OutputInput/OutputInput/OutputInput/OutputADC1 through ADC7 input pins are reserved for future use but can beused for I/O or other designated functions.In SelectMAP mode, D0 through D31 are configuration data pins. These pinsbecome user I/Os after configuration, unless the SelectMAP port is retained.These lower capacitance clock pins connect to Clock Capable I/Os. Thesepins do not support LVDS outputs, and they become regular user I/Oswhen not needed for clocks.These lower capacitance clock pins connect to Global Clock Buffers. Thesepins do not support LVDS outputs, and they become regular user I/Oswhen not needed for clocks. For single-ended clock inputs, use P-side pinsonly.14 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008
RPin DefinitionsTable 1-3: Virtex-4 FPGA Pin Definitions (Continued)Pin Name Direction DescriptionLC (2) Input/Output These lower capacitance pins do not support LVDS outputs.SMnV REFVRNVRPInput/OutputInput/OutputInput/OutputInput/OutputSM1 through SM7 input pins are reserved for future use but can be usedfor I/O or other designated functions.These are input threshold voltage pins. They become user I/Os when anexternal threshold voltage is not needed (per bank).This pin is for the DCI voltage reference resistor of N transistor (per bank,to be pulled High with reference resistor).This pin is for the DCI voltage reference resistor of P transistor (per bank,to be pulled Low with reference resistor).Dedicated Configuration Pins (1)CCLK_0Input/OutputConfiguration clock. Output and input in Master mode or Input in Slavemode.CS_B_0 Input In SelectMAP mode, this is the active-low Chip Select signal.D_IN_0 Input In bit-serial modes, D_IN is the single-data input.DONE_0DOUT_BUSY_0Input/OutputOutputDONE is a bidirectional signal with an optional internal pull-up resistor.As an output, this pin indicates completion of the configuration process.As an input, a Low level on DONE can be configured to delay the start-upsequence.In SelectMAP mode, BUSY controls the rate at which configuration data isloaded.In bit-serial modes, DOUT gives preamble and configuration data to downstreamdevices in a daisy chain.HSWAPEN Input Enable I/O pull-ups during configurationINIT_B_0Bidirectional(open-drain)When Low, this pin indicates that the configuration memory is beingcleared. When held Low, the start of configuration is delayed. Duringconfiguration, a Low on this output indicates that a configuration dataerror has occurred.M0_0, M1_0, M2_0 Input Configuration mode selectionPROG_B_0PWRDWN_B_0InputInput(unsupported)Active Low asynchronous reset to configuration logic. This pin has apermanent weak pull-up resistor.Active Low power-down pin (unsupported). Driving this pin Low canadversely affect device operation and configuration. PWRDWN_B is internallypulled High, which is its default state. It does not require an external pull-up.Do not connect this pin to GND; leave it floating or pull it up to V CC .RDWR_B_0 Input In SelectMAP mode, this is the active-low Write Enable signal.TCK_0 Input Boundary-Scan ClockTDI_0 Input Boundary-Scan Data InputTDO_0 Output Boundary-Scan Data OutputVirtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 15UG075 (v3.3) September 19, 2008
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Page 4: Virtex-4 FPGA Packaging and Pinout
Page 7 and 8: RPrefaceAbout This GuideOrganizatio
Page 9 and 10: RTypographical ConventionsTypograph
Page 11 and 12: RChapter 1Packaging OverviewSummary
Page 13: RDevice/Package Combinations and Ma
Page 17 and 18: RPin DefinitionsTable 1-3: Virtex-4
Page 19 and 20: RChapter 2Pinout TablesSummaryThis
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RChapter 3Pinout DiagramsSummaryThi
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RSF363 Package Pinout Diagram (LX15
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RSF363 Color-Coded SelectIO and Ban
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RFF668 Package Pinout Diagram (LX25
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RChapter 6Package MarkingVirtex-4 D
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