Xilinx UG075 Virtex-4 FPGA Packaging and Pinout Specification ...

RChapter 1Packaging OverviewSummaryIntroductionThis chapter covers the following topics:• Introduction• Device/Package Combinations and Maximum I/Os• Pin DefinitionsThis section describes the pinouts for Virtex-4 devices in the 0.80 mm and 1.00 mm pitchflip-chip fine-pitch BGA packages.Virtex-4 devices are offered exclusively in high performance flip-chip BGA packages thatare optimally designed for improved signal integrity and jitter. Package inductance isminimized as a result of optimal placement and even distribution, as well as an increasednumber, of Power and GND pins.All of the devices supported in a particular package are pinout compatible and are listed inthe same table (one table per package). Pins that are not available for the smaller devicesare listed in the “No Connects” column of each table. VCCO_# pins listed as “NoConnects” can be required for larger devices. This must be considered when migrating intoa larger part within the same package.Each device is split into eight or more I/O banks to allow for flexibility in the choice of I/Ostandards (see the Virtex-4 FPGA User Guide). Global pins, including JTAG, configuration,and power/ground pins, are listed at the end of each table. Table 1-3 provides definitionsfor all pin types.For the very latest Virtex-4 FPGA pinout information, visit www.xilinx.com and check forany updates to this document.Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 11UG075 (v3.3) September 19, 2008