A Compiler for Parallel Exeuction of Numerical Python Programs on ...

2.1.1 SIMD unitsEach SIMD unit is composed <strong>of</strong> the following:1. 16 thread processors (TP). Each TP is a VLIW unit that can execute one 5-wide VeryLong Instruction Word (VLIW) instructions each cycle. Each TP contains five ALUs.AMD calls each ALU as stream processor (SP). Each SP can execute one fp32 or oneint32 multiply-and-add (MAD) operation per cycle. One <strong>of</strong> the five SPs in a TP isa “fat” SP and only the fat SP can execute transcendental functions such as sin orcos. Thus, the peak per<strong>for</strong>mance <strong>of</strong> a TP is ten fp32 FLOPs per cycle. For fp64, thescenario is more complex. The four non-fat ALUs co-operate to execute a single fp64MAD instruction each cycle and thus the fp64 peak <strong>of</strong> each TP is two FLOPs/cycleor 1/5th <strong>of</strong> the fp32 peak. If the compiler is unable to pack 5 instructions into onepacket, then the peak is not achieved because each TP is a VLIW processor.2. Each SIMD has a huge register file with 64×256 float4/int4 registers. The registersare untyped with four 32-bit components. Each component <strong>of</strong> a register can eitherstore a floating-point value or an integer value. Two components <strong>of</strong> a register can becombined to store a double-precision value. The register file is arranged in sixteenblocks <strong>of</strong> four banks each. This gives a total <strong>of</strong> 64 banks and each bank can do onefloat4 transfer per cycle. Thus the bandwidth to the register file is 1024 bytes/cycle.The peak transfer rate from the register file is less than the peak demand <strong>of</strong> the ALUs.This is explained by the fact that there exists a <strong>for</strong>warding path where a TP can usea result computed in a previous cycle.3. A 16-Kbyte shared memory called the local data share (LDS). The LDS is arranged infour banks, each with 256 128-bit entries. Each bank can do one 128-bit transfer percycle. Thus the LDS can transfer 64 bytes/cycle. There<strong>for</strong>e, the bandwidth from theLDS is much smaller than the bandwidth from the register file. The size and layout <strong>of</strong>the register file suggests that it is very similar to one block <strong>of</strong> a register file but withadditional indexing hardware.2.1.2 Texture unitsEach texture unit can compute four addresses per cycle. There<strong>for</strong>e, the ten texture unitscan calculate a total <strong>of</strong> 40 addresses per cycle. Each texture unit has a dedicated L1 cache.The size <strong>of</strong> the L1 cache has not been published by AMD. Each texture unit is aligned withand services exactly one SIMD unit. Given that an SIMD can execute 800 ALU operationsor equivalently 1600 FLOPs per cycle, the asymmetry in the ALU:TEX ratio is apparent.The texture unit provides many facilities, such as filtering, but those are typically not usedin compute workloads and are thus not discussed in this thesis.7