A Compiler for Parallel Exeuction of Numerical Python Programs on ...

2.3 Hardware execution model2.3.1 Pixel shadersThe programmer can specify millions <strong>of</strong> threads to be executed. However not all threadsare executed at the same time on the GPU. In pixel-shader mode, the hardware dividesthe two-dimensional grid <strong>of</strong> threads into groups <strong>of</strong> 8×8 thread groups called wavefronts.An SIMD runs one or more wavefronts in parallel. The wavefront sizes vary from GPUto GPU: it is 64 on the RV770 but it is 32 on the RV730. A wavefront starts executingon an SIMD and continues executing until it encounters a non-ALU instruction (such as atexture related instruction). Then the wavefront is swapped out and replaced with anotherwavefront while the original non-ALU wavefront is sent back to be scheduled on the unitrequired to complete the instruction that it is waiting on. Thus the GPU uses the massiveparallelism to hide the latency <strong>of</strong> memory loads.The number <strong>of</strong> wavefronts that can be run in parallel on an SIMD in pixel-shader modeis decided by the availability <strong>of</strong> registers. If R denotes the number <strong>of</strong> registers required perthread, W denotes the wavefront size (64 on RV770), N is the number <strong>of</strong> wavefronts runningin parallel and P is the number <strong>of</strong> physical registers in the register file, then N = P/(W ∗R).The driver is responsible <strong>for</strong> partitioning the physical register file among all the runningwavefronts. When a wavefront is swapped out from an ALU to a texture unit, the registersbeing used by the wavefront are still retained in the register file until the wavefront finishesexecution.For RV770, the wavefront size <strong>of</strong> 64 is four times the number <strong>of</strong> thread processors perSIMD. Thus each thread processor is running four threads in parallel and is likely to hidethe latency <strong>of</strong> ALU units. The register file is divided into banks <strong>of</strong> 64 and thus I speculatethat each thread in a wavefront reads and writes to exactly one bank.2.3.2 Compute shadersCompute shaders are similar to pixel shaders in most respects. To execute a compute shader,64 continuous thread-ids in a thread are chosen as a wavefront. The maximum number <strong>of</strong>wavefronts that can run in parallel in a compute shader is determined by the number <strong>of</strong>registers used per thread as well as the amount <strong>of</strong> local data share owned by each thread.Shared registersThe register file in a compute shader is used not only <strong>for</strong> the per-thread registers butalso <strong>for</strong> shared registers. Shared registers are registers shared amongst threads in a threadgroup. However shared registers have the restriction that the register is actually only sharedbetween threads n, n+64, n+128.. and so on within a thread group. Thus thread 0 andthread 1 within a thread group do not actually see the same register. Instead there are 6412