A Compiler for Parallel Exeuction of Numerical Python Programs on ...

approach, the number <strong>of</strong> elements transferred is 6 ∗ 5 ∗ 2 = 60 elements. The ERL approachcan result in significant savings in the number <strong>of</strong> elements transferred if only a small tile <strong>of</strong>a large array is accessed in a computation.If the number <strong>of</strong> dimensions is greater than one, then a feasible solution does not necessarilyexist. The problem is that we are attempting to interpret the n RCSLMADs as ninterleaved accesses into a d-dimensional array but such an interpretation does not alwaysexist. If the integer programming solver is called and no feasible solution is found, then thecompiler falls back to algorithm 3 <strong>for</strong> data transfer analysis.To generate the mapped address <strong>of</strong> each array access, algorithm 5 is used.Algorithm 5 computes the mapped address <strong>for</strong> multidimensional RCSLMAD problemssolved using the integer linear programming methodInputs: Specified constants u k , values t mk and b ′ m computed using integer linearprogramming Outputs: A list <strong>of</strong> n expressions representing the address on theGPU.1: Construct a vector R1 = [b ′ 1, b ′ 2, ..., b ′ n].2: Construct a vector R2 = R1.3: Remove all non-duplicate entries <strong>of</strong> R2.4: Sort R2 in-place.5: Construct a vector R3 such that R3[i] = x where R2[x] = R1[i].6: Compute q = length <strong>of</strong> R2.7: <strong>for</strong> each integer k such that 1 ≤ k ≤ d do8: Compute t k = max(t 1k , t 2k , ..., t nk ).9: end <strong>for</strong>10: Compute b 0 = min(R1).11: <strong>for</strong> each RCSLMAD L m dod∑d∏12: Construct an expression I m = (b ′ m − b 0 ) + q ∗ (i k + t mk ) ∗ (u l + t l ).13: end <strong>for</strong>14: return list {I 1 , I 2 , ..., I n }.k=1l=k+15.4 Loop tiling <strong>for</strong> handling large loopsUsing previously discussed algorithms 3 and 5, the number <strong>of</strong> elements to be transferred tothe GPU can be computed. However, if the amount <strong>of</strong> memory to be transferred does not fiton the GPU, then the compiler must attempt to tile the loop. In the implemented compiler,the compiler only considers tiling the parallel loops since tiling parallel loops is always legal.Once an acceptable tile size is found, then the tiles are executed sequentially on the GPU.The execution <strong>of</strong> the tiles can be pipelined but this possibility was not considered due totime constraints.In the ideal case, the tiling should be such that the total amount <strong>of</strong> data transferredbetween the CPU and GPU should be minimized. However, again the problem is hard andthere<strong>for</strong>e a very basic heuristic was used. The compiler simply reduces the upper bound <strong>of</strong>47