Chapter 2 Real-Time Systems Concepts Foreground/Background ...

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Interrupt latency, Response, and Recovery• The most important specification of a real-time kernel is theamount of time interrupts are disabled– The longer interrupts are disabled , the higher the interrupt latency• Interrupt latency– Maximum amount of time interrupts are disabled + Time to startexecuting the first instruction in the ISR• Interrupt response (defined as the time between the reception of theinterrupt and the start of the user code that handles the interrupt)– Foreground/background Interrupt latency + Time to save the CPU's context– Non-preemptive kernel (don’t need to disable interrupt)– Preemptive kernelInterrupt latency + Time to save the CPU's context +Execution time of the kernel ISR entry function• Interrupt recovery (the time required for the processor to return to the interrupted code)– Foreground/background Time to restore the CPU's context +– Non-preemptive kernelTime to execute the return from interrupt instruction– Preemptive kernelTime to determine if a higher priority task is ready +Time to restore the CPU's context of the highest priority task + 2-43Time to execute the return from interrupt instructionFigure 2.20 foreground/backgroundInterrupt RequestTIMEBACKGROUNDBACKGROUNDCPU Context SavedISRUser ISR CodeCPU contextrestoredInterrupt LatencyInterrupt ResponseInterrupt Recovery2-44
Figure 2.21 non-preemptive kernelInterrupt RequestTIMETASKTASKCPU Context SavedISRUser ISR CodeCPU contextrestoredInterrupt LatencyInterrupt ResponseInterrupt Recovery2-45Figure 2.22 preemptive kernelTIMEInterrupt RequestInterrupt RecoveryTASKTASKCPU Context SavedKernel's ISRExit functionAISRKernel's ISREntry functionUser ISR CodeCPU contextrestoredInterrupt LatencyInterrupt ResponseKernel's ISRExit functionCPU contextrestoredBTASKInterrupt Recovery2-46
Page 1 and 2: Chapter 2Real-Time Systems Concepts
Page 3 and 4: • Resource- EX: I/O, CPU, Memory,
Page 5 and 6: • Foreground/background programmi
Page 7 and 8: Scheduler• Also called the dispat
Page 9 and 10: Figure 2.5 Preemptive kernelLow Pri
Page 11 and 12: Figure 2.7 Priority Inversion probl
Page 13 and 14: • Disabling and enabling interrup
Page 15 and 16: • Accessing shared data by obtain
Page 17 and 18: BUF * BufReq(void){BUF *ptr;Acquire
Page 19 and 20: Event Flags (uCOS-II does not suppo
Page 21: Message queues• Is used to send o
Page 25 and 26: Clock Tick• A special interrupt t
Page 27: • Reduce the execution jitter of

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