ModelSim SE Tutorial

Basic simulation flow T-13Basic simulation flowThe following diagram shows the basic steps for simulating a design in ModelSim.Create a working libraryCompile design filesRun simulationDebug resultsCreating the working libraryIn ModelSim, all designs, be they VHDL, Verilog, SystemC, or some combination thereof, are compiled into a library. Youtypically start a new simulation in ModelSim by creating a working library called "work". "Work" is the library name used by thecompiler as the default destination for compiled design units.Compiling your designAfter creating the working library, you compile your design units into it. The ModelSim library format is compatible across allsupported platforms. You can simulate your design on any platform without having to recompile your design.Running the simulationWith the design compiled, you invoke the simulator on a top-level module (Verilog) or a configuration or entity/architecture pair(VHDL). Assuming the design loads successfully, the simulation time is set to zero, and you enter a run command to beginsimulation.ModelSim SE Tutorial