11.07.2015 Views

ModelSim SE Tutorial

ModelSim SE Tutorial

ModelSim SE Tutorial

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T-20 Lesson 2 - Basic simulationIntroductionIn this lesson you will go step-by-step through the basic simulation flow:Create a working libraryCompile design unitsRun simulationDebug resultsDesign files for this lessonThe sample design for this lesson is a simple 8-bit, binary up-counter with anassociated testbench. The pathnames are as follows:Verilog – /modeltech/examples/counter.v and tcounter.vVHDL – /modeltech/examples/counter.vhd and tcounter.vhdThis lesson uses the Verilog files counter.v and tcounter.v in the examples. If youhave a VHDL license, use counter.vhd and tcounter.vhd instead. Or, if you havea mixed license, feel free to use the Verilog testbench with the VHDL counter orvice versa.Related reading<strong>ModelSim</strong> User’s Manual – Chapter 3 - Design libraries (UM-55), Chapter 5 -Verilog simulation (UM-109), Chapter 4 - VHDL simulation (UM-69)<strong>ModelSim</strong> Command Reference (vlib (CR-361), vmap (CR-375), vlog (CR-363),vcom (CR-316), vopt (CR-376), view (CR-337), and right (CR-255) commands)<strong>ModelSim</strong> <strong>SE</strong> <strong>Tutorial</strong>

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