VHDL Implementation of Reversible Logic Gates - ijater

vector respectively. The block diagram of a 3*3 NEWGATE is shown in Fig. 2.10.International Journal of Advanced Technology & Engineering Research (IJATER)Figure 2.12: 3X3 PERES GATEFigure 2.10: 3*3 NEW GATE.Figure 2.13: combinational circuit diagram of 3x3 PERESGATEFigure 2.11: combinational circuit diagram of 3x3 NEWGATELibrary ieee;Use ieee std_logic.1164..all;Entity newg isPort(A, B, C : in std_logic;P, Q, R : out std_logic);end newg;architecture ckt of newg issignal Abar, Bbar, Cbar, S1, S2 : std_logic;beginP

International Journal of Advanced Technology & Engineering Research (IJATER)Library ieee;Use ieee std_logic.1164..all;Entity trg isPort(A, B, C : in std_logic;P, Q, R : out std_logic);end trg;architecture ckt of trg issignal Bbar, S1: std_logic;beginP

International Journal of Advanced Technology & Engineering Research (IJATER)S2

International Journal of Advanced Technology & Engineering Research (IJATER)[11] Peres, A. 1985. Reversible logic and quantumcomputers. Physical Review A, 32: 3266-3276.[12] M.S.Islam et al., “low Cost Quantum RealizationOf Reversible Multiplier Circuit”, InformationTechnology Journal, 8(2008)208.[13] H.R. Bhagyalakshmi and M.K. Venkatesha,“Optimized Reversible BCD Adder Using NewReversible Logic Gates” Lournal of Computing,Volume 2, Feb 2010. ISSN 2151-9617 arXiv.3994v1[14] Bhagyalakshmi, H.R. ;.Venkatesha, M.K, „Animproved design of a multiplier using reversible logicgates‟, International Journal of Engineering Science andTechnology Vol. 2(8), 2010, 3838-3845.[15] Krishnaveni. D, Geeta priya, M, “ Design of anefficient reversible 8*8 wallau tree multiplier,”Submitted for Review to ckts and system-1 Journal,IEEE.[16] Michael P. Frank, Reversibility for efficientcomputing, Ph. D. Thesis, May 1999.http://www.cise.ufl.edu/-mpf/rc/thesis /phdthesis.html.[17] Michael P. Frank Reversible Computing Page.[18] Carlin Vieri, Reversible Computing for EnergyEfficient and Trustable computation, April 1998,Of Engineering for Women, Jaipur. . She has presented apaper In International Conference held in Janardan Rai NagarRajasthan Vidyapeeth (D) University Udaipur, April 2012 on“4-BIT REVERSILE FULLADDER USING DKG GATEIMPLEMENTATION IN VHDL.” And a paper presented inNational Conference held in MITRC Alwar, April 2012on “Reversible Full Adder Gate using Nano-Technology”. Her current area of research includesREVERSIBLE TECHNOLOGY & Data Encryptionand currently working on the project related to it.Biographies:Devendra Goyal (devagoyal87@gmail.com,devagoyal@yahoo.co.in) has received his B.E.Degree in 2009 Electronics & CommunicationEngineering from MIT, KOTA & now pursuing M.Tech in VLSI DESIGN from Poornima College OfEngineering Jaipur. He has presented a paper In InternationalConference held in Janardan Rai Nagar Rajasthan Vidyapeeth(D) University Udaipur, April 2012 on “4-BIT REVERSILEFULLADDER USING DKG GATE IMPLEMENTATIONIN VHDL.” And a paper presented in National Conferenceheld in MITRC Alwar, April 2012 on “Reversible FullAdder Gate using Nano-Technology” His current areaof research includes REVERSIBLE TECHNOLOGYand currently working on the project related to it.Vidhi Sharma (sharmavidhif7@gmail.com) hasreceived his B.E. Degree in 2009 Electronics &Communication Engineering from R.N.MODI, KOTA& now pursuing M. Tech in Electronics &Communication Engineering from Rajasthan CollegeISSN NO: 2250-3536 VOLUME 2, ISSUE 2, MAY 2012 163