VHDL Implementation of Reversible Logic Gates - ijater
VHDL Implementation of Reversible Logic Gates - ijater
VHDL Implementation of Reversible Logic Gates - ijater
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vector respectively. The block diagram <strong>of</strong> a 3*3 NEWGATE is shown in Fig. 2.10.International Journal <strong>of</strong> Advanced Technology & Engineering Research (IJATER)Figure 2.12: 3X3 PERES GATEFigure 2.10: 3*3 NEW GATE.Figure 2.13: combinational circuit diagram <strong>of</strong> 3x3 PERESGATEFigure 2.11: combinational circuit diagram <strong>of</strong> 3x3 NEWGATELibrary ieee;Use ieee std_logic.1164..all;Entity newg isPort(A, B, C : in std_logic;P, Q, R : out std_logic);end newg;architecture ckt <strong>of</strong> newg issignal Abar, Bbar, Cbar, S1, S2 : std_logic;beginP
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