VHDL Implementation of Reversible Logic Gates - ijater
VHDL Implementation of Reversible Logic Gates - ijater
VHDL Implementation of Reversible Logic Gates - ijater
You also want an ePaper? Increase the reach of your titles
YUMPU automatically turns print PDFs into web optimized ePapers that Google loves.
International Journal <strong>of</strong> Advanced Technology & Engineering Research (IJATER)[11] Peres, A. 1985. <strong>Reversible</strong> logic and quantumcomputers. Physical Review A, 32: 3266-3276.[12] M.S.Islam et al., “low Cost Quantum RealizationOf <strong>Reversible</strong> Multiplier Circuit”, InformationTechnology Journal, 8(2008)208.[13] H.R. Bhagyalakshmi and M.K. Venkatesha,“Optimized <strong>Reversible</strong> BCD Adder Using New<strong>Reversible</strong> <strong>Logic</strong> <strong>Gates</strong>” Lournal <strong>of</strong> Computing,Volume 2, Feb 2010. ISSN 2151-9617 arXiv.3994v1[14] Bhagyalakshmi, H.R. ;.Venkatesha, M.K, „Animproved design <strong>of</strong> a multiplier using reversible logicgates‟, International Journal <strong>of</strong> Engineering Science andTechnology Vol. 2(8), 2010, 3838-3845.[15] Krishnaveni. D, Geeta priya, M, “ Design <strong>of</strong> anefficient reversible 8*8 wallau tree multiplier,”Submitted for Review to ckts and system-1 Journal,IEEE.[16] Michael P. Frank, Reversibility for efficientcomputing, Ph. D. Thesis, May 1999.http://www.cise.ufl.edu/-mpf/rc/thesis /phdthesis.html.[17] Michael P. Frank <strong>Reversible</strong> Computing Page.[18] Carlin Vieri, <strong>Reversible</strong> Computing for EnergyEfficient and Trustable computation, April 1998,Of Engineering for Women, Jaipur. . She has presented apaper In International Conference held in Janardan Rai NagarRajasthan Vidyapeeth (D) University Udaipur, April 2012 on“4-BIT REVERSILE FULLADDER USING DKG GATEIMPLEMENTATION IN <strong>VHDL</strong>.” And a paper presented inNational Conference held in MITRC Alwar, April 2012on “<strong>Reversible</strong> Full Adder Gate using Nano-Technology”. Her current area <strong>of</strong> research includesREVERSIBLE TECHNOLOGY & Data Encryptionand currently working on the project related to it.Biographies:Devendra Goyal (devagoyal87@gmail.com,devagoyal@yahoo.co.in) has received his B.E.Degree in 2009 Electronics & CommunicationEngineering from MIT, KOTA & now pursuing M.Tech in VLSI DESIGN from Poornima College OfEngineering Jaipur. He has presented a paper In InternationalConference held in Janardan Rai Nagar Rajasthan Vidyapeeth(D) University Udaipur, April 2012 on “4-BIT REVERSILEFULLADDER USING DKG GATE IMPLEMENTATIONIN <strong>VHDL</strong>.” And a paper presented in National Conferenceheld in MITRC Alwar, April 2012 on “<strong>Reversible</strong> FullAdder Gate using Nano-Technology” His current area<strong>of</strong> research includes REVERSIBLE TECHNOLOGYand currently working on the project related to it.Vidhi Sharma (sharmavidhif7@gmail.com) hasreceived his B.E. Degree in 2009 Electronics &Communication Engineering from R.N.MODI, KOTA& now pursuing M. Tech in Electronics &Communication Engineering from Rajasthan CollegeISSN NO: 2250-3536 VOLUME 2, ISSUE 2, MAY 2012 163
Change language