Packaging Nano Wafer Level - National University of Singapore

NanoWafer LevelPackaging"Nano Chips Need Nano Packaging"Prof. Rao R. TummalaTemasek Professor, NUS, SingaporeDirector, Packaging Research Center,Georgia Tech, USAAn International Collaborationin Research and EducationNational University of SingaporeInstitute of Microelectronics, SingaporeGeorgia Institute of Technology, USAProf. Andrew TayNUS, Program ManagerDr. Mahadevan K. IyerIME, Program ManagerResearch Area Georgia Tech NUS IMEElectrical Design M. Swaminathan Simon Ang Mahadevan K. IyerMaterials &ProcessesC.P. WongAshok SaxenaSuresh SitaramanE.T. KangK.G. NeohManoj GuptaAndrew TaySimon AngY.C. LiangV. KripeshWong Ee HuaCelaine WongMarvin LoTest & Burn-inDavid KeezerSimon AngW.K. WongMihai RotaruReliabilitySuresh SitaramanAndrew TayC.T. LimK.M. LimW.K. WongWong Ee Hua100 Micron BoardVenky SundaramV. KripeshMarvin LoIntegrated TestbedDavid KeezerM. SwaminathanVenky SundaramC.P. WongAndrew TaySimon AngET KangW.K. WongMahadevan K. IyerV. KripeshWong Ee HuaMihai RotaruResearch Staff &Students2 Post DoctoralAssociates12 GraduateStudents3 Post Doctoral Fellows, 2 ResearchEngineers, 16 Graduate Students,5 Research Staff

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Electrical DesignObjectives: Maintaining signal integrity represents one of the major bottlenecksfor enabling reliable systems. This is due to the increase in speed, reduction involtage, increase in power, and the integration of mixed signal functions in futuresystems. Examples of such systems include electro-optic USB interfaces,wireless devices, server farms and computing applications. Due to the fasttransition of digital signals, the analog behavior of these signals becomes veryimportant. Issues such as cross talk, reflections, switching noise, eye patternsand delay, therefore, have to be addressed for the design of systems. Wafer levelpackaging of circuits provides a very attractive solution for future micro-systems,especially in the mobile computing area. This is because of reduced parasiticsand smaller form factor.Approach: The combination of wafer level packaging and a high-density printedcircuit board with embedded functionality has many advantages for the design ofmixed signal Nano systems. The wafer level package reduces parasitics throughshort compliant or rigid leads, improves isolation by separating incompatiblecircuitry and enables much better matching of components for developingintegrated solutions. Both modeling and experimental techniques will bepursued. In particular, the following electrical issues will be studied in detail: 1)design of the chip-to-package compliant or rigid leads and transitions forsupporting digital and RF signals 20-50GHz; 2) design of the chip-to-packagecompliant and rigid leads to supply >200W of power to the chips with minimumpower supply noise and electro-migration problems and; 3) study of transmissionline and radiation effects of the chip-to-package compliant or rigid leads forsupporting 20-50GHz digital signals.Research Focus:Design of the transitions from the chip into the high-density printed circuitboard through the compliant or rigid leads. Modeling tools and measurementtechniques will be used for the design of these transitions.3Design of the compliant or rigid leads with minimum inductance that cansupport fast transient currents for supporting multi-gigahertz digital circuitsdissipating > 200W of power. Power distribution analysis tools developed atGeorgia Tech will be enhanced to model the geometries. These will becorrelated with measurements on custom chips.Modeling of the current density through the compliant or rigid leads toestimate high frequency current densities and their effect on electromigration.Radiation and transmission line measurements to better understand theelectromagnetic behavior of the leads at frequencies 20-50GHz.

Design, Modeling and ReliabilityModeling, Assessment & EvaluationStructuralAnalysisReliabilityTestVehicleMechanicalTest andEvaluationObjectives: With the continued reduction in IC feature size and with theincreased demand for better performance and lower cost, there is a need for aninnovative, yet reliable, interconnect technology. According to the NTRSroadmap in the U.S., the interconnect pitch, will be less than 50 microns, and inselect opto-electronic applications, it can be as small as 10 microns. Most of theexisting interconnect technologies today, even with dramatic improvements, areincapable of addressing this ultra-fine pitch requirement. Therefore, there is acompelling need to understand theModel Designsfor Reliabilitythermo-mechanical designrequirements, failure mechanisms andreliability of such interconnects anddevelop suitable interconnects startingwith design for reliability.4Materials CharacterizationReliability Modeling & VerificationGeneral Interconnection Design and Optimization SchemeTestDesignsVerifyDesignApproach: To cater to the CTEmismatch between the die and thesubstrate, two basic designs of ultra-finepitch interconnections have beenproposed: compliant and rigid. Acompliant interconnection reduces thestress but tends to yield lower electricalperformance and mechanical flimsinesscompared to rigid interconnections. On the other hand, rigid interconnectionshave to sustain higher stresses resulting in likely failures by fracture or fatigue.However, this deficiency may be overcome by the use of high-strength Nanostructuredmaterials. The mechanical, thermal and electrical characteristics ofvarious interconnection designs falling under the two main categories will bestudied extensively through modeling and simulation and a few likely-to-succeeddesigns will be identified. Specimens of the short-listed designs will then befabricated and the material properties and processes characterized. Constitutivemodels of new materials will be obtained. The state of stress in theinterconnections will be modeled for the entire fabrication process in order topredict more precisely the reliability of the final product. Extensive reliability testswill also be conducted in order to study the failure mechanisms operating. Modelsof these failure mechanisms will be developed and used to predict the reliabilityof the final product. With such models developed, the design of theinterconnections can be further optimized through simulation and experimentalverification.Research Focus:Design:- Propose potential solutions for 100 micron and 20 micron pitches;- Critical evaluation of characteristics and challenges of each solution.Modeling:- Develop methodology for modeling material properties and processes;- Develop comprehensive models to predict failure mechanisms operating;- Develop integrated modeling methodology and design for reliability ofWLP;- Explore the use of molecular dynamics and multi-scale modeling inreliability prediction of WLP.Materials Characterization:- Conduct experiments to characterize the properties of materials includingNano-structured materials;- Develop constitutive models of relevant materials.Failure Analysis and Reliability Tests:- Design and conduct reliability tests to study the operative failuremechanisms;- Develop failure analysis techniques and methodology to characterize thefailure mechanisms;- Demonstrate reliability of testbed.

Wafer Level Interconnect ApproachesObjectives: The overall objective is to develop fine pitch and low costinterconnect technologies for high-density wafer level packaging. The currentwafer level packages are at a pitch of 300-400 microns, serving primarily memoryproducts. The proposed pitch will explore different wafer level interconnecttechnologies for 20 micron and demonstrate 100 micron pitch meeting theelectrical, thermal and mechanical requirements.Approach: With the need of 20 to 100 micron pitch, both rigid and compliantinterconnect structures will be pursued in this thrust area. A total of 6 differentwafer level interconnect schemes are proposed:a) 100 micron pitch- Bed of nails (compliant)- Streched solder column (rigid)- Lead-free solder balls with no flow underfill (rigid)b) 20 micron pitch- Nanostructured interconnect based on polymer-metal or metal-metalinterfacial composites (rigid)- Nano links- MEMs-fabricated interconnects (compliant)The wafer level packages with 100 micron pitch will be assembled into the finalintegrated test bed. The wafer level packages with 20 micron pitch incorporatesNano interconnects and will be studied form a research point of view.Research Focus:Explore and demonstrate promising materials and processes for 20 micronand 100 micron pitch wafer level interconnect schemes;5Select or develop metal and lead-free solder alloys and develop newcharacterization methodologies;Develop the processes involved in fabricating the interconnections;Optimize various processes for 100 micron scheme.100 Micron Pitch: 20 Micron Pitch:Silicon ChipSilicon ChipHigh Density BoardVery High Density BoardBed ofNailsStretchedSolderColumnSolder Ballswith No FlowUnderfillNanoLinksMEMSInterconnectNanoInterconnectWafer Level Interconnect Scheme

Potential of Nano-Structured MaterialsObjectives: The most aggressive wafer level packaging proposed is on 20micron pitch. At this pitch, the conventional solder ball technology does notguarantee the reliability of the IC-to-board joint. Compliant connection is onesolution but it may be expensive and it may not provide the best electricalproperties. Underfill around the solder is another solution but it makes theprocess complex and makes the technology expensive too. Nanointerconnection is proposed because of its potential unique mechanical andelectrical properties.Approach: Experimental studies have demonstrated that there is considerablepotential for enhancing strength of materials through interface strengthening(increasing grain boundary area and/or phase boundary area) in several materialsystems such as Cu, Ni, Ni-base alloys and intermetallics, aluminum alloys, gold,and carbon steels. Mechanical strengthening in crystalline materials occurs as aresult of obstacles encountered by dislocations restricting their mobility.Obstacles to dislocation motion are in the form of (a) lack of appropriate numberof primary slip systems (b) coherent and incoherent precipitates (c) interphaseand antiphase boundaries and (d) grain boundaries. Thus, reducingmicrostructural features to the Nanometer scale and creating more suchobstacles in the process, provides avenues for tailoring strength, toughness, andcreep properties, in addition to influencing electrical resistivity and solid-statediffusivity and solubility.Research Focus:6Identify promising Nano-stuctured materials systems for use in 20 micronpitch interconnects and produce them in experimental quantities forevaluation. The range of materials to be considered include monolithicmetals and alloys as well as composites containing Nano-structured metalsand alloys as particulate reinforcements and conductive polymers as matrix;Characterize the materials to obtain tensile strength, hardness, fracturetoughness and fatigue properties, and electrical properties, using noveltechniques such as Nano indentation, in-situ AFM/STEM, SEM. Developnew characterization techniques as needed;Develop modeling and simulation tools to extract most information fromtests and to aid in developing in-depth understanding of phenomena at theNano level for its fullest exploitation in wafer level interconnect applications.Intercept grain diameter, nm10 4 10 3 10 2 10Vickers Microhardness, kg/mm 2800600400200Nickel Electroplate0 100 200 300Reciprocal square root of grain size, nm 2Microhardness of electroplated nickel as a function of reciprocalof the square root of grain size (Neiman, Weertman, and Siegel, 1991)

Test and Burn-In SystemObjectives: Wafer level packaging is incomplete without guaranteeing KnownGood Die (KGD). In conventional IC packaging it is done by test and burn in afterthe IC is packaged as QFP, BGA or CSP. But this individual test and burn-in atthe IC level is a sequential and expensive process. The objective of this task is todevelop strategies and implement them at 100 micron pitch at wafer level.Approach: The need to make electrical contacts to the interconnectingstructures with pitches of 20-100 microns presents tremendous challenges.Furthermore, the bandwidth requirements present tremendous challenges to theselection of materials as well as integration and fabrication methods. Presently,testing of wafer-level packaged devices is performed using fine-pitch probesdirectly on the wafer. It is expected that this approach will not be applicable tothe Nano wafer level.Test WorkStationMeasurementInstrumentTest Signal ProcessorInterposerD.U.T.WaferProbing CardAn interposer, with a self-aligned, z-axis compliant and good electrical contactfeatures, will be designed and fabricated to serve as the electrical andmechanical interface between the N-WLP and the tester. Due to the largenumber of inputs/outputs on this N-WLP (in the order of 10,000 to 200,000 I/Osper cm 2 , it is anticipated that this interposer will not be able to handle therequired re-distribution task. As such, a test support processor (TSP) boardconsisting of a field-programmable array device, memory devices, sample-andholddevices, clocks, multiplexers, and others, will be integrated onto the top layerof the interposer, using the flip chip attachment method. The test signalprocessor will act as the tester with the required test stimuli and memory tocapture the tested data. In this way, only a few I/Os from the TSP are required foreach wafer level-packaged device.A burn-in system that simultaneously connects devices on several N-WLP ICswill also be developed. As in most burn-in requirements, the task of redistributingthe vast number of I/Os may not be the limiting factor as only specificelectrical connections are required during burn-in. An interposer, similar to theinterposer developed for wafer-level test, will be developed to serve as theelectrical and mechanical interface for burn-in.Wafer D.U.T.7Research Focus: Besides fabrication challenges, the other major challengeswill be the selection of materials and integration methods to meet the largebandwidth requirements of the interposer.Design and fabrication of the interposerDesign and fabrication of the test signal processorIntegration of the test signal processor onto the interposer to form theTSP interposerTest and characterization of the TSP interposerDesign and fabrication of a burn-in interposerIntegration of the burn-in interposer into a burn-in systemOptimization of test and burn-in strategy for NWLP

Integrated Wafer Level Test BedObjectives: The objective is to design and assemble an integrated test bed todemonstrate 100 micron pitch reliable wafer level packaged system. The test bedshall integrate all the above wafer level packaging technologies including the testand burn-in to mee the required mechanical and electrical integrity.Approach: The approach would be to integrate all the enabling technologies intoa testbed. The proposed specification for 100 micron pitch wafer level packageswill be designed into the testbed. The challenges from electrical signal integrityand thermo-mechanical reliability would be addressed in the 100 micron pitchtestbed design and development. The testbed is also intended to demonstrate thewafer level packaging materials and processes. The electrical testing will be donein two phases: 1) DC testing, demonstrating the technologies; and 2) functionaltesting, demonstrating the test features and compatibility of the technology totesting.Proposed Target Specification of the Nano Wafer Level PackagesSpecification: Present: Proposed:Specification: State of the Art Today: Proposed: 100 Micron Proposed: 20 MIcron100 micron 20 micronAcceptable Cost U.S. $50 to $150 0.5X 0.1XElectrical Digital and RF Digital and RF Digital and RF2-3 GHz 10 GHz 20-50 GHzThermomechanical JEDEC Level 3 JEDEC Level 2ReliabilityBoard Level Reliability8Die Size 7mm (0.8 sq. cm) 20 mm (4 sq. cm) 20 mm (4 sq. cm)Pitch 50 µm 100 µm 20 µmDistance from Neutral Point 10,000Interconnect Size 300 µm 30 µm 6-8 µmApplications Memories, Passives, RF-Ids Handheld Computing High Performance ComputingManufacturability Batch Processing Batch Processing Batch ProcessingEnbabling Technology RDL, UBM Comliant, Rigid Nano InterconnectTest and Burn-inMaterials Characterization,Processes,Test and Burn-inResearch Focus:Develop electrical design and simulation methodologies ofthe test bed to accommodate 100 micron pitch wafer levelpackages. The design and characterization techniques usedat the wafer level interconnects would be extended to thesystem test bed keeping in mind the 20-50GHz bandwidthgoal;Exploration and assessment of the thermo-mechanicalreliability.DC level testing and burn-in integrated into the board. Thetest strategies developed at the wafer level would beextended to board level testing;Design and development of 100 micron board demonstratingthe compatibility between the 100 micron pitch wafer and the100 micron board.

Enquiries and Contacts:Professor Andrew Tay, Department of Mechanical Engineering,National University of Singapore, 9 Engineering Drive 1, Singapore 117576.Email: mpetayao@nus.edu.sgCarl Rust, Associate Director, Packaging Research CenterGeorgia Institute of Technology, 813 Ferst Drive, Room 351, Atlanta GA 30332 U.S.A.Email: crust@ee.gatech.eduDr. Mahadevan K. Iyer, R&D Manager, Advanced Packaging Development SupportInstitute of Microelectronics, 11 Science Park Road Singapore Science Park II Singapore 117685Email: iyer@ime.org.sgWebsites of Collaborating Institutions:National University of Singapore:http://www.nus.edu.sgInstitute of Microelectronics, Singapore:http://www.ime.org.sgPackaging Research Center, Georgia Tech, USA: http://www.prc.gatech.edu