Packaging Nano Wafer Level - National University of Singapore
Packaging Nano Wafer Level - National University of Singapore
Packaging Nano Wafer Level - National University of Singapore
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<strong>Nano</strong><strong>Wafer</strong> <strong>Level</strong><strong>Packaging</strong>"<strong>Nano</strong> Chips Need <strong>Nano</strong> <strong>Packaging</strong>"Pr<strong>of</strong>. Rao R. TummalaTemasek Pr<strong>of</strong>essor, NUS, <strong>Singapore</strong>Director, <strong>Packaging</strong> Research Center,Georgia Tech, USAAn International Collaborationin Research and Education<strong>National</strong> <strong>University</strong> <strong>of</strong> <strong>Singapore</strong>Institute <strong>of</strong> Microelectronics, <strong>Singapore</strong>Georgia Institute <strong>of</strong> Technology, USAPr<strong>of</strong>. Andrew TayNUS, Program ManagerDr. Mahadevan K. IyerIME, Program ManagerResearch Area Georgia Tech NUS IMEElectrical Design M. Swaminathan Simon Ang Mahadevan K. IyerMaterials &ProcessesC.P. WongAshok SaxenaSuresh SitaramanE.T. KangK.G. NeohManoj GuptaAndrew TaySimon AngY.C. LiangV. KripeshWong Ee HuaCelaine WongMarvin LoTest & Burn-inDavid KeezerSimon AngW.K. WongMihai RotaruReliabilitySuresh SitaramanAndrew TayC.T. LimK.M. LimW.K. WongWong Ee Hua100 Micron BoardVenky SundaramV. KripeshMarvin LoIntegrated TestbedDavid KeezerM. SwaminathanVenky SundaramC.P. WongAndrew TaySimon AngET KangW.K. WongMahadevan K. IyerV. KripeshWong Ee HuaMihai RotaruResearch Staff &Students2 Post DoctoralAssociates12 GraduateStudents3 Post Doctoral Fellows, 2 ResearchEngineers, 16 Graduate Students,5 Research Staff
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