Packaging Nano Wafer Level - National University of Singapore

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Design, Modeling and ReliabilityModeling, Assessment & EvaluationStructuralAnalysisReliabilityTestVehicleMechanicalTest andEvaluationObjectives: With the continued reduction in IC feature size and with theincreased demand for better performance and lower cost, there is a need for aninnovative, yet reliable, interconnect technology. According to the NTRSroadmap in the U.S., the interconnect pitch, will be less than 50 microns, and inselect opto-electronic applications, it can be as small as 10 microns. Most of theexisting interconnect technologies today, even with dramatic improvements, areincapable of addressing this ultra-fine pitch requirement. Therefore, there is acompelling need to understand theModel Designsfor Reliabilitythermo-mechanical designrequirements, failure mechanisms andreliability of such interconnects anddevelop suitable interconnects startingwith design for reliability.4Materials CharacterizationReliability Modeling & VerificationGeneral Interconnection Design and Optimization SchemeTestDesignsVerifyDesignApproach: To cater to the CTEmismatch between the die and thesubstrate, two basic designs of ultra-finepitch interconnections have beenproposed: compliant and rigid. Acompliant interconnection reduces thestress but tends to yield lower electricalperformance and mechanical flimsinesscompared to rigid interconnections. On the other hand, rigid interconnectionshave to sustain higher stresses resulting in likely failures by fracture or fatigue.However, this deficiency may be overcome by the use of high-strength Nanostructuredmaterials. The mechanical, thermal and electrical characteristics ofvarious interconnection designs falling under the two main categories will bestudied extensively through modeling and simulation and a few likely-to-succeeddesigns will be identified. Specimens of the short-listed designs will then befabricated and the material properties and processes characterized. Constitutivemodels of new materials will be obtained. The state of stress in theinterconnections will be modeled for the entire fabrication process in order topredict more precisely the reliability of the final product. Extensive reliability testswill also be conducted in order to study the failure mechanisms operating. Modelsof these failure mechanisms will be developed and used to predict the reliabilityof the final product. With such models developed, the design of theinterconnections can be further optimized through simulation and experimentalverification.Research Focus:Design:- Propose potential solutions for 100 micron and 20 micron pitches;- Critical evaluation of characteristics and challenges of each solution.Modeling:- Develop methodology for modeling material properties and processes;- Develop comprehensive models to predict failure mechanisms operating;- Develop integrated modeling methodology and design for reliability ofWLP;- Explore the use of molecular dynamics and multi-scale modeling inreliability prediction of WLP.Materials Characterization:- Conduct experiments to characterize the properties of materials includingNano-structured materials;- Develop constitutive models of relevant materials.Failure Analysis and Reliability Tests:- Design and conduct reliability tests to study the operative failuremechanisms;- Develop failure analysis techniques and methodology to characterize thefailure mechanisms;- Demonstrate reliability of testbed.
Wafer Level Interconnect ApproachesObjectives: The overall objective is to develop fine pitch and low costinterconnect technologies for high-density wafer level packaging. The currentwafer level packages are at a pitch of 300-400 microns, serving primarily memoryproducts. The proposed pitch will explore different wafer level interconnecttechnologies for 20 micron and demonstrate 100 micron pitch meeting theelectrical, thermal and mechanical requirements.Approach: With the need of 20 to 100 micron pitch, both rigid and compliantinterconnect structures will be pursued in this thrust area. A total of 6 differentwafer level interconnect schemes are proposed:a) 100 micron pitch- Bed of nails (compliant)- Streched solder column (rigid)- Lead-free solder balls with no flow underfill (rigid)b) 20 micron pitch- Nanostructured interconnect based on polymer-metal or metal-metalinterfacial composites (rigid)- Nano links- MEMs-fabricated interconnects (compliant)The wafer level packages with 100 micron pitch will be assembled into the finalintegrated test bed. The wafer level packages with 20 micron pitch incorporatesNano interconnects and will be studied form a research point of view.Research Focus:Explore and demonstrate promising materials and processes for 20 micronand 100 micron pitch wafer level interconnect schemes;5Select or develop metal and lead-free solder alloys and develop newcharacterization methodologies;Develop the processes involved in fabricating the interconnections;Optimize various processes for 100 micron scheme.100 Micron Pitch: 20 Micron Pitch:Silicon ChipSilicon ChipHigh Density BoardVery High Density BoardBed ofNailsStretchedSolderColumnSolder Ballswith No FlowUnderfillNanoLinksMEMSInterconnectNanoInterconnectWafer Level Interconnect Scheme
Page 2: NanoWafer LevelPackaging"Nano Chips
Page 5: Electrical DesignObjectives: Mainta
Page 9 and 10: Test and Burn-In SystemObjectives:
Page 11: Enquiries and Contacts:Professor An

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