Packaging Nano Wafer Level - National University of Singapore

Potential of Nano-Structured MaterialsObjectives: The most aggressive wafer level packaging proposed is on 20micron pitch. At this pitch, the conventional solder ball technology does notguarantee the reliability of the IC-to-board joint. Compliant connection is onesolution but it may be expensive and it may not provide the best electricalproperties. Underfill around the solder is another solution but it makes theprocess complex and makes the technology expensive too. Nanointerconnection is proposed because of its potential unique mechanical andelectrical properties.Approach: Experimental studies have demonstrated that there is considerablepotential for enhancing strength of materials through interface strengthening(increasing grain boundary area and/or phase boundary area) in several materialsystems such as Cu, Ni, Ni-base alloys and intermetallics, aluminum alloys, gold,and carbon steels. Mechanical strengthening in crystalline materials occurs as aresult of obstacles encountered by dislocations restricting their mobility.Obstacles to dislocation motion are in the form of (a) lack of appropriate numberof primary slip systems (b) coherent and incoherent precipitates (c) interphaseand antiphase boundaries and (d) grain boundaries. Thus, reducingmicrostructural features to the Nanometer scale and creating more suchobstacles in the process, provides avenues for tailoring strength, toughness, andcreep properties, in addition to influencing electrical resistivity and solid-statediffusivity and solubility.Research Focus:6Identify promising Nano-stuctured materials systems for use in 20 micronpitch interconnects and produce them in experimental quantities forevaluation. The range of materials to be considered include monolithicmetals and alloys as well as composites containing Nano-structured metalsand alloys as particulate reinforcements and conductive polymers as matrix;Characterize the materials to obtain tensile strength, hardness, fracturetoughness and fatigue properties, and electrical properties, using noveltechniques such as Nano indentation, in-situ AFM/STEM, SEM. Developnew characterization techniques as needed;Develop modeling and simulation tools to extract most information fromtests and to aid in developing in-depth understanding of phenomena at theNano level for its fullest exploitation in wafer level interconnect applications.Intercept grain diameter, nm10 4 10 3 10 2 10Vickers Microhardness, kg/mm 2800600400200Nickel Electroplate0 100 200 300Reciprocal square root of grain size, nm 2Microhardness of electroplated nickel as a function of reciprocalof the square root of grain size (Neiman, Weertman, and Siegel, 1991)