Packaging Nano Wafer Level - National University of Singapore

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Potential of Nano-Structured MaterialsObjectives: The most aggressive wafer level packaging proposed is on 20micron pitch. At this pitch, the conventional solder ball technology does notguarantee the reliability of the IC-to-board joint. Compliant connection is onesolution but it may be expensive and it may not provide the best electricalproperties. Underfill around the solder is another solution but it makes theprocess complex and makes the technology expensive too. Nanointerconnection is proposed because of its potential unique mechanical andelectrical properties.Approach: Experimental studies have demonstrated that there is considerablepotential for enhancing strength of materials through interface strengthening(increasing grain boundary area and/or phase boundary area) in several materialsystems such as Cu, Ni, Ni-base alloys and intermetallics, aluminum alloys, gold,and carbon steels. Mechanical strengthening in crystalline materials occurs as aresult of obstacles encountered by dislocations restricting their mobility.Obstacles to dislocation motion are in the form of (a) lack of appropriate numberof primary slip systems (b) coherent and incoherent precipitates (c) interphaseand antiphase boundaries and (d) grain boundaries. Thus, reducingmicrostructural features to the Nanometer scale and creating more suchobstacles in the process, provides avenues for tailoring strength, toughness, andcreep properties, in addition to influencing electrical resistivity and solid-statediffusivity and solubility.Research Focus:6Identify promising Nano-stuctured materials systems for use in 20 micronpitch interconnects and produce them in experimental quantities forevaluation. The range of materials to be considered include monolithicmetals and alloys as well as composites containing Nano-structured metalsand alloys as particulate reinforcements and conductive polymers as matrix;Characterize the materials to obtain tensile strength, hardness, fracturetoughness and fatigue properties, and electrical properties, using noveltechniques such as Nano indentation, in-situ AFM/STEM, SEM. Developnew characterization techniques as needed;Develop modeling and simulation tools to extract most information fromtests and to aid in developing in-depth understanding of phenomena at theNano level for its fullest exploitation in wafer level interconnect applications.Intercept grain diameter, nm10 4 10 3 10 2 10Vickers Microhardness, kg/mm 2800600400200Nickel Electroplate0 100 200 300Reciprocal square root of grain size, nm 2Microhardness of electroplated nickel as a function of reciprocalof the square root of grain size (Neiman, Weertman, and Siegel, 1991)
Test and Burn-In SystemObjectives: Wafer level packaging is incomplete without guaranteeing KnownGood Die (KGD). In conventional IC packaging it is done by test and burn in afterthe IC is packaged as QFP, BGA or CSP. But this individual test and burn-in atthe IC level is a sequential and expensive process. The objective of this task is todevelop strategies and implement them at 100 micron pitch at wafer level.Approach: The need to make electrical contacts to the interconnectingstructures with pitches of 20-100 microns presents tremendous challenges.Furthermore, the bandwidth requirements present tremendous challenges to theselection of materials as well as integration and fabrication methods. Presently,testing of wafer-level packaged devices is performed using fine-pitch probesdirectly on the wafer. It is expected that this approach will not be applicable tothe Nano wafer level.Test WorkStationMeasurementInstrumentTest Signal ProcessorInterposerD.U.T.WaferProbing CardAn interposer, with a self-aligned, z-axis compliant and good electrical contactfeatures, will be designed and fabricated to serve as the electrical andmechanical interface between the N-WLP and the tester. Due to the largenumber of inputs/outputs on this N-WLP (in the order of 10,000 to 200,000 I/Osper cm 2 , it is anticipated that this interposer will not be able to handle therequired re-distribution task. As such, a test support processor (TSP) boardconsisting of a field-programmable array device, memory devices, sample-andholddevices, clocks, multiplexers, and others, will be integrated onto the top layerof the interposer, using the flip chip attachment method. The test signalprocessor will act as the tester with the required test stimuli and memory tocapture the tested data. In this way, only a few I/Os from the TSP are required foreach wafer level-packaged device.A burn-in system that simultaneously connects devices on several N-WLP ICswill also be developed. As in most burn-in requirements, the task of redistributingthe vast number of I/Os may not be the limiting factor as only specificelectrical connections are required during burn-in. An interposer, similar to theinterposer developed for wafer-level test, will be developed to serve as theelectrical and mechanical interface for burn-in.Wafer D.U.T.7Research Focus: Besides fabrication challenges, the other major challengeswill be the selection of materials and integration methods to meet the largebandwidth requirements of the interposer.Design and fabrication of the interposerDesign and fabrication of the test signal processorIntegration of the test signal processor onto the interposer to form theTSP interposerTest and characterization of the TSP interposerDesign and fabrication of a burn-in interposerIntegration of the burn-in interposer into a burn-in systemOptimization of test and burn-in strategy for NWLP
Page 2: NanoWafer LevelPackaging"Nano Chips
Page 5 and 6: Electrical DesignObjectives: Mainta
Page 7: Wafer Level Interconnect Approaches
Page 11: Enquiries and Contacts:Professor An

Packaging Nano Wafer Level - National University of Singapore

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