Ultra Low Power Stereo Audio Codec (Rev. A

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TLV320AIC3204Ultra Low Power Stereo Audio CodecSLOS602A–SEPTEMBER 2008–REVISED OCTOBER 2008www.ti.com6.2.5 Page 0 / Register 4: Clock Setting Register 1, MultiplexersBITREAD/WRITERESETVALUED7 R 0 Reserved, Write only default valuesD6 R/W 0 Select PLL Range0: Low PLL Clock Range1: High PLL Clock RangeDESCRIPTIOND5–D4 R 00 Reserved, Write only default values any other value than reset value.D3–D2 R/W 00 Select PLL Input Clock00: MCLK pin is input to PLL01: BCLK pin is input to PLL10: GPIO pin is input to PLL11: DIN pin is input to PLLD1–D0 R/W 00 Select CODEC_CLKIN00: MCLK pin is CODEC_CLKIN01: BCLK pin is CODEC_CLKIN10: GPIO pin is CODEC_CLKIN11: PLL Clock is CODEC_CLKIN6.2.6 Page 0 / Register 5: Clock Setting Register 2, PLL P&R ValuesBITREAD/WRITERESETVALUED7 R/W 0 PLL Power Up0: PLL is powered down1: PLL is powered upD6–D4 R/W 001 PLL divider P Value000: P=8001: P=1010: P=2…110: P=6111: P=7D3–D0 R/W 0001 PLL divider R Value000: Reserved, do not use001: R=1010: R=2011: R=3100: R=4101…111: Reserved, do not useDESCRIPTION6.2.7 Page 0 / Register 6: Clock Setting Register 3, PLL J ValuesBITREAD/WRITERESETVALUEDESCRIPTIOND7–D6 R 00 Reserved. Write only default values any value other than defaultD5–D0 R/W 00 0100 PLL divider J value00 0000…00 0011: Do not use00 0100: J=400 0101: J=5…11 1110: J=6211 1111: J=636.2.8 Page 0 / Register 7: Clock Setting Register 4, PLL D Values (MSB)BITREAD/WRITERESETVALUEDESCRIPTIOND7–D6 R 00 Reserved. Write only default values any value other than default104 REGISTER MAPSubmit Documentation Feedback
6.2.9 Page 0 / Register 8: Clock Setting Register 5, PLL D Values (LSB)TLV320AIC3204Ultra Low Power Stereo Audio Codecwww.ti.com SLOS602A–SEPTEMBER 2008–REVISED OCTOBER 2008BITREAD/WRITERESETVALUE(continued)DESCRIPTIOND5–D0 R/W 00 0000 PLL divider D value (MSB)PLL divider D value(MSB) & PLL divider D value(LSB)00 0000 0000 0000: D=000000 0000 0000 0001: D=0001…10 0111 0000 1110: D=999810 0111 0000 1111: D=999910 0111 0001 0000…11 1111 1111 1111: Do not useNote: This register will be updated only when the Page-0, Reg-8 is written immediately afterPage-0, Reg-7BITREAD/WRITERESETVALUEDESCRIPTIOND7–D0 R/W 0000 0000 PLL divider D value (LSB)PLL divider D value(MSB) & PLL divider D value(LSB)00 0000 0000 0000: D=000000 0000 0000 0001: D=0001…10 0111 0000 1110: D=999810 0111 0000 1111: D=999910 0111 0001 0000…11 1111 1111 1111: Do not useNote: Page-0, Reg-8 should be written immediately after Page-0, Reg-76.2.10 Page 0 / Register 9-10: Reserved RegisterREAD/ RESETBITWRITE VALUED7–D0 R 0000 0000 Reserved, Write only default values.DESCRIPTION6.2.11 Page 0 / Register 11: Clock Setting Register 6, NDAC ValuesBITREAD/WRITERESETVALUED7 R/W 0 NDAC Divider Power Control0: NDAC divider powered down1: NDAC divider powered upDESCRIPTIOND6–D0 R/W 000 0001 NDAC Value000 0000: NDAC=128000 0001: NDAC=1000 0010: NDAC=2…111 1110: NDAC=126111 1111: NDAC=127Note: Please check the clock frequency requirements in the Overview section6.2.12 Page 0 / Register 12: Clock Setting Register 7, MDAC ValuesBITREAD/WRITERESETVALUED7 R/W 0 MDAC Divider Power Control0: MDAC divider powered down1: MDAC divider powered upDESCRIPTIOND6–D0 R/W 000 0001 MDAC Value000 0000: MDAC=128000 0001: MDAC=1000 0010: MDAC=2…111 1110: MDAC=126111 1111: MDAC=127Note: Please check the clock frequency requirements in the Overview sectionSubmit Documentation Feedback REGISTER MAP 105
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LDO inLDO SelectAVddDVddIOVddAVssDV
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LORLOLIN3_RIN3_LMICBIASREFTLV320AIC
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TLV320AIC3204Ultra Low Power Stereo
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3.3 ELECTRICAL CHARACTERISTICSTLV32
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Page 11 and 12:
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All numbers are from characterizati
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3.4.3.2 TYPICAL TIMING CHARACTERIST
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4 TYPICAL CHARACTERISTICS4.1 TYPICA
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4.2 FFTTLV320AIC3204Ultra Low Power
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5 Application Information5.1 TYPICA
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5.2.6 Register Settings for Multifu
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5.3 ANALOG ROUTINGTLV320AIC3204Ultr
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5.5 POWERTUNE5.5.1 PowerTune Modes5
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5.5.2.4 ADC, Mono, 48kHz, Highest P
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5.5.2.9 ADC, Stereo, 8kHz, Lowest P
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5.5.2.14 ADC, Stereo, 192kHz, Lowes
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5.5.3.2 DAC, Stereo, 48kHz, Lowest
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5.5.3.6 DAC, Stereo, 8kHz, Lowest P
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5.5.3.10 DAC, Stereo, 192kHz, Lowes
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5.7.2 Digital Volume Control5.7.3 F
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NH(z) 2023 N D11z11zTLV320AIC3204Ul
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5.8 ADC Decimation Filtering and Si
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5.8.2.5 3 Biquads, 1 st order IIR,
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5.8.3.2 Biquad SectionNH(z) 2023 2
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5.8.4.1 Decimation Filter ATLV320AI
Page 53 and 54: 5.8.4.3 Decimation Filter CTLV320AI
Page 55 and 56: TLV320AIC3204Ultra Low Power Stereo
Page 57 and 58: 5.9.7 Adaptive FilteringTLV320AIC32
Page 61 and 62: 5.11.1 Processing BlocksTLV320AIC32
Page 63 and 64: 5.11.2.6 4 Biquads, Filter BTLV320A
Page 65 and 66: 5.11.3 User Programmable Filters5.1
Page 71 and 72: 5.12.2 Headphone Amplifier Class-D
Page 75 and 76: 5.13.3.1 DRC Threshold5.13.3.2 DRC
Page 77 and 78: 5.14.2 DIGITAL AUTO MUTE5.14.3 Adap
Page 79 and 80: 5.16 CLOCK GENERATION AND PLLTLV320
Page 83 and 84: 5.16.1 PLLTLV320AIC3204Ultra Low Po
Page 85 and 86: 5.17 INTERFACE5.17.1 AUDIO DIGITAL
Page 91 and 92: 5.17.2.1 I 2 C CONTROL MODETLV320AI
Page 95 and 96: 5.18.1.3 Other Supply Options5.19 R
Page 99 and 100: 5.22.3 DAC Playback Through Class-D
Page 101 and 102: 5.22.5 Stereo ADC with 48ksps Sampl
Page 103: 6 REGISTER MAP6.1 Register Map Summ
Page 107 and 108: 6.2.19 Page 0 / Register 19: Clock
Page 109 and 110: 6.2.29 Page 0 / Register 29: Audio
Page 111 and 112: 6.2.36 Page 0 / Register 36: ADC Fl
Page 113 and 114: 6.2.43 Page 0 / Register 45: Sticky
Page 117 and 118: 6.2.54 Page 0 / Register 57-59: Res
Page 119 and 120: 6.2.61 Page 0 / Register 66: Right
Page 121 and 122: 6.2.67 Page 0 / Register 72: Beep G
Page 125 and 126: 6.2.85 Page 0 / Register 90: Left C
Page 129 and 130: 6.2.98 Page 0 / Register 103: DC Me
Page 131 and 132: 6.2.109 Page 1 / Register 3: Playba
Page 133 and 134: 6.2.117 Page 1 / Register 14: LOL R
Page 145 and 146: 6.2.141 Page 1 / Register 62: ADC A
Page 147 and 148: 6.2.152 Page 9-16 / Register 0: Pag
Page 149 and 150: 6.2.167 Page 62-70 / Register 8-127
Page 153 and 154: PACKAGE OPTION ADDENDUMwww.ti.com26
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PACKAGE MATERIALS INFORMATIONwww.ti
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