Ultra Low Power Stereo Audio Codec (Rev. A

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TLV320AIC3204Ultra Low Power Stereo Audio CodecSLOS602A–SEPTEMBER 2008–REVISED OCTOBER 2008www.ti.comNote: All timing specifications are measured at characterization but not tested at final test.WCLKt (WS) dt (WS) dBCLKDOUTt (DO-BCLK)dt (DI) st (DI) hDIN3.4.3.1 TYPICAL TIMING CHARACTERISTICS (see Figure 3-3)All specifications at 25°C, DVdd = 1.8VFigure 3-3. DSP Timing in Master ModeTable 3-3. DSP Timing in Master ModePARAMETER IOVDD=1.8V IOVDD=3.3V UNITSMIN MAX MIN MAXt d (WS) WCLK delay 30 20 nst d (DO-BCLK) BCLK to DOUT delay 22 20 nst s (DI) DIN setup 8 8 nst h (DI) DIN hold 8 8 nst r Rise time 24 12 nst f Fall time 24 12 nsNote: All timing specifications are measured at characterization but not tested at final test.WCLKt (ws) ht (ws) st (ws) ht (ws) hBCLKDOUTt (BCLK) Ht (BCLK) Pt (BCLK) Lt (DO-BCLK)dt (DI) st (DI) hDINFigure 3-4. DSP Timing in Slave Mode14 Electrical SpecificationsSubmit Documentation Feedback
3.4.3.2 TYPICAL TIMING CHARACTERISTICS (see Figure 3-4)All specifications at 25°C, DVdd = 1.8VTLV320AIC3204Ultra Low Power Stereo Audio Codecwww.ti.com SLOS602A–SEPTEMBER 2008–REVISED OCTOBER 2008Table 3-4. DSP Timing in Slave ModePARAMETER IOVDD=1.8V IOVDD=3.3V UNITSMIN MAX MIN MAXt H (BCLK) BCLK high period 35 35 nst L (BCLK) BCLK low period 35 35 nst s (WS) WCLK setup 8 8 nst h (WS) WCLK hold 8 8 nst d (DO-BCLK) BCLK to DOUT delay 22 22 nst s (DI) DIN setup 8 8 nst h (DI) DIN hold 8 8 nst r Rise time 4 4 nst f Fall time 4 4 nsNote: All timing specifications are measured at characterization but not tested at final test.3.4.4 I 2 C INTERFACE TIMINGFigure 3-5.Table 3-5. I 2 C INTERFACE TIMINGPARAMETER TEST CONDITION Standard-Mode Fast-Mode UNITSMIN TYP MAX MIN TYP MAXf SCL SCL clock frequency 0 100 0 400 kHzt HD;STA Hold time (repeated) START 4.0 0.8 µscondition. After this period, the firstclock pulse is generated.t LOW LOW period of the SCL clock 4.7 1.3 µst HIGH HIGH period of the SCL clock 4.0 0.6 µst SU;STA Setup time for a repeated START 4.7 0.8 µsconditiont HD;DAT Data hold time: For I2C bus 0 3.45 0 0.9 µsdevicest SU;DAT Data set-up time 250 100 nst r SDA and SCL Rise Time 1000 20+0.1C b 300 nst f SDA and SCL Fall Time 300 20+0.1C b 300 nst SU;STO Set-up time for STOP condition 4.0 0.8 µst BUF Bus free time between a STOP 4.7 1.3 µsand START conditionC b Capacitive load for each bus line 400 400 pFSubmit Documentation Feedback Electrical Specifications 15
Page 1 and 2: LDO inLDO SelectAVddDVddIOVddAVssDV
Page 3 and 4: LORLOLIN3_RIN3_LMICBIASREFTLV320AIC
Page 5 and 6: TLV320AIC3204Ultra Low Power Stereo
Page 7 and 8: 3.3 ELECTRICAL CHARACTERISTICSTLV32
Page 13: All numbers are from characterizati
Page 17 and 18: 4 TYPICAL CHARACTERISTICS4.1 TYPICA
Page 19 and 20: 4.2 FFTTLV320AIC3204Ultra Low Power
Page 21 and 22: 5 Application Information5.1 TYPICA
Page 23 and 24: 5.2.6 Register Settings for Multifu
Page 25 and 26: 5.3 ANALOG ROUTINGTLV320AIC3204Ultr
Page 27 and 28: 5.5 POWERTUNE5.5.1 PowerTune Modes5
Page 29 and 30: 5.5.2.4 ADC, Mono, 48kHz, Highest P
Page 31 and 32: 5.5.2.9 ADC, Stereo, 8kHz, Lowest P
Page 33 and 34: 5.5.2.14 ADC, Stereo, 192kHz, Lowes
Page 35 and 36: 5.5.3.2 DAC, Stereo, 48kHz, Lowest
Page 37 and 38: 5.5.3.6 DAC, Stereo, 8kHz, Lowest P
Page 39 and 40: 5.5.3.10 DAC, Stereo, 192kHz, Lowes
Page 41 and 42: 5.7.2 Digital Volume Control5.7.3 F
Page 43 and 44: NH(z) 2023 N D11z11zTLV320AIC3204Ul
Page 45 and 46: 5.8 ADC Decimation Filtering and Si
Page 47 and 48: 5.8.2.5 3 Biquads, 1 st order IIR,
Page 49 and 50: 5.8.3.2 Biquad SectionNH(z) 2023 2
Page 51 and 52: 5.8.4.1 Decimation Filter ATLV320AI
Page 53 and 54: 5.8.4.3 Decimation Filter CTLV320AI
Page 57 and 58: 5.9.7 Adaptive FilteringTLV320AIC32
Page 61 and 62: 5.11.1 Processing BlocksTLV320AIC32
Page 63 and 64: 5.11.2.6 4 Biquads, Filter BTLV320A
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5.11.3 User Programmable Filters5.1
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TLV320AIC3204Ultra Low Power Stereo
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5.12.2 Headphone Amplifier Class-D
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5.13.3.1 DRC Threshold5.13.3.2 DRC
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5.14.2 DIGITAL AUTO MUTE5.14.3 Adap
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5.16 CLOCK GENERATION AND PLLTLV320
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5.16.1 PLLTLV320AIC3204Ultra Low Po
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5.17 INTERFACE5.17.1 AUDIO DIGITAL
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5.17.2.1 I 2 C CONTROL MODETLV320AI
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5.18.1.3 Other Supply Options5.19 R
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5.22.3 DAC Playback Through Class-D
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5.22.5 Stereo ADC with 48ksps Sampl
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6 REGISTER MAP6.1 Register Map Summ
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6.2.9 Page 0 / Register 8: Clock Se
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6.2.19 Page 0 / Register 19: Clock
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6.2.29 Page 0 / Register 29: Audio
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6.2.36 Page 0 / Register 36: ADC Fl
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6.2.43 Page 0 / Register 45: Sticky
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6.2.54 Page 0 / Register 57-59: Res
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6.2.61 Page 0 / Register 66: Right
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6.2.67 Page 0 / Register 72: Beep G
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6.2.85 Page 0 / Register 90: Left C
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6.2.98 Page 0 / Register 103: DC Me
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6.2.109 Page 1 / Register 3: Playba
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6.2.117 Page 1 / Register 14: LOL R
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6.2.141 Page 1 / Register 62: ADC A
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6.2.152 Page 9-16 / Register 0: Pag
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6.2.167 Page 62-70 / Register 8-127
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PACKAGE OPTION ADDENDUMwww.ti.com26
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PACKAGE MATERIALS INFORMATIONwww.ti
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Ultra Low Power Stereo Audio Codec (Rev. A

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