Ultra Low Power Stereo Audio Codec (Rev. A

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TLV320AIC3204Ultra Low Power Stereo Audio CodecSLOS602A–SEPTEMBER 2008–REVISED OCTOBER 2008www.ti.comLINE INPUT TO LINE-OUT FFT @ 446mVrmsvsFREQUENCY0-20-40Power - dBr-60-80-100-120-1400 5000 10000 15000 20000f - Frequency - HzFigure 4-12.20 TYPICAL CHARACTERISTICS Submit Documentation Feedback
5 Application Information5.1 TYPICAL CIRCUIT CONFIGURATIONTLV320AIC3204Ultra Low Power Stereo Audio Codecwww.ti.com SLOS602A–SEPTEMBER 2008–REVISED OCTOBER 2008Host ProcessorResetMCLKSCL SDA BCLK WCLK DIN DOUT1k1k2.7kSPI_SelectMICBIASLOL1K4700p0.1u0.1u0.1uF0.1uFIN1_RIN1_LTLV320AIC3204LOR1K4700p0.1u0.1uTPA2012Class D Amp0.1uF0.1uFIN2_LLDOIN0.1uF 1.0uF 10uF1.9...3.6VIN2_R1k1k1.1...3.6VMFP3/SCLKIOVDD0.1uFIN3_RLDO_SELECTHeadset_MicHPRHPLAVSS DVSS IOVSSAVDDDVDDREFEarjackmicrophoneand headsetspeakersHeadset_Spkr_R 47uFHeadset_Spkr_LHeadset_Gnd 47uF10 uF10 uF 10 uFFigure 5-1. Typical Circuit Configuration5.2 OVERVIEWThe TLV320AIC3204 offers a wide range of configuration options. Figure 1-1 shows the basic functionalblocks of the device.5.2.1 Digital PinsOnly a small number of digital pins are dedicated to a single function; whenever possible, the digital pinshave a default function, and also can be reprogrammed to cover alternative functions for variousapplications.The fixed-function pins are Reset , LDO_Select and the SPI_Select pin, which are HW control pins.Depending on the state of SPI_Select, the two control-bus pins SCL/SSZ and SDA/MOSI are configuredfor either I 2 C or SPI protocol.Other digital IO pins can be configured for various functions via register control. An overview of availablefunctionality is given in Section 5.2.5 below.Submit Documentation Feedback Application Information 21
Page 1 and 2: LDO inLDO SelectAVddDVddIOVddAVssDV
Page 3 and 4: LORLOLIN3_RIN3_LMICBIASREFTLV320AIC
Page 5 and 6: TLV320AIC3204Ultra Low Power Stereo
Page 7 and 8: 3.3 ELECTRICAL CHARACTERISTICSTLV32
Page 13 and 14: All numbers are from characterizati
Page 15 and 16: 3.4.3.2 TYPICAL TIMING CHARACTERIST
Page 17 and 18: 4 TYPICAL CHARACTERISTICS4.1 TYPICA
Page 19: 4.2 FFTTLV320AIC3204Ultra Low Power
Page 23 and 24: 5.2.6 Register Settings for Multifu
Page 25 and 26: 5.3 ANALOG ROUTINGTLV320AIC3204Ultr
Page 27 and 28: 5.5 POWERTUNE5.5.1 PowerTune Modes5
Page 29 and 30: 5.5.2.4 ADC, Mono, 48kHz, Highest P
Page 31 and 32: 5.5.2.9 ADC, Stereo, 8kHz, Lowest P
Page 33 and 34: 5.5.2.14 ADC, Stereo, 192kHz, Lowes
Page 35 and 36: 5.5.3.2 DAC, Stereo, 48kHz, Lowest
Page 37 and 38: 5.5.3.6 DAC, Stereo, 8kHz, Lowest P
Page 39 and 40: 5.5.3.10 DAC, Stereo, 192kHz, Lowes
Page 41 and 42: 5.7.2 Digital Volume Control5.7.3 F
Page 43 and 44: NH(z) 2023 N D11z11zTLV320AIC3204Ul
Page 45 and 46: 5.8 ADC Decimation Filtering and Si
Page 47 and 48: 5.8.2.5 3 Biquads, 1 st order IIR,
Page 49 and 50: 5.8.3.2 Biquad SectionNH(z) 2023 2
Page 51 and 52: 5.8.4.1 Decimation Filter ATLV320AI
Page 53 and 54: 5.8.4.3 Decimation Filter CTLV320AI
Page 57 and 58: 5.9.7 Adaptive FilteringTLV320AIC32
Page 61 and 62: 5.11.1 Processing BlocksTLV320AIC32
Page 63 and 64: 5.11.2.6 4 Biquads, Filter BTLV320A
Page 65 and 66: 5.11.3 User Programmable Filters5.1
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5.12.2 Headphone Amplifier Class-D
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TLV320AIC3204Ultra Low Power Stereo
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5.13.3.1 DRC Threshold5.13.3.2 DRC
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5.14.2 DIGITAL AUTO MUTE5.14.3 Adap
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5.16 CLOCK GENERATION AND PLLTLV320
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5.16.1 PLLTLV320AIC3204Ultra Low Po
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5.17 INTERFACE5.17.1 AUDIO DIGITAL
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5.17.2.1 I 2 C CONTROL MODETLV320AI
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5.18.1.3 Other Supply Options5.19 R
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5.22.3 DAC Playback Through Class-D
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5.22.5 Stereo ADC with 48ksps Sampl
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6 REGISTER MAP6.1 Register Map Summ
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6.2.9 Page 0 / Register 8: Clock Se
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6.2.19 Page 0 / Register 19: Clock
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6.2.29 Page 0 / Register 29: Audio
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6.2.36 Page 0 / Register 36: ADC Fl
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6.2.43 Page 0 / Register 45: Sticky
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6.2.54 Page 0 / Register 57-59: Res
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6.2.61 Page 0 / Register 66: Right
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6.2.67 Page 0 / Register 72: Beep G
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6.2.85 Page 0 / Register 90: Left C
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6.2.98 Page 0 / Register 103: DC Me
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6.2.109 Page 1 / Register 3: Playba
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6.2.117 Page 1 / Register 14: LOL R
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6.2.141 Page 1 / Register 62: ADC A
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6.2.152 Page 9-16 / Register 0: Pag
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6.2.167 Page 62-70 / Register 8-127
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PACKAGE OPTION ADDENDUMwww.ti.com26
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PACKAGE MATERIALS INFORMATIONwww.ti
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