FICON Express2 Channel Performance Version 1.0 - IBM

FICON Express2 Channel Performance Version 1.0
Page 14
Figure 13 shows the FICON Express2 channel PCI bus utilizations for this same 6x27K
Read/Write mix benchmark. PCI bus utilizations are the bus utilizations reported on the
RMF Channel activity report for FICON Express2 channels but there is another internal
channel bus whose utilization is roughly 1.5 to 2 times the PCI bus utilization. This internal
channel bus is the real resource that limits the 6x27K Read/Write benchmark from achieving
higher than 270MB/sec but it is highly unlikely that any real production workload would
come anywhere near approaching this limit. For real production workloads, the most
relevant resource limits to pay attention to are the channel and the control unit processor and
link limits and these are the limits that I have highlighted for each benchmark measurement
result presented in this paper.
z990 FEx2 6x27K Read/write mix
FICON Bus Utilization(FBU) vs MB/sec
FICON bus utilization (FBU)
100
90
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70
60
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40
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0
0 30 60 90 120 150 180 210 240 270 300
Total READ + WRITE MB/sec
Figure 13
FEx2 FBU
Figures 14 and 15 represent two different ways of looking at the results of the 27K or
half-track read hit benchmark. The first figure below is a plot of response times and FICON
processor utilizations vs. io/sec. Here we see a sharp increase in response times just over
6000 io/sec and at about 60% FICON processor utilization (FPU). The second 27K read hit
graph plots response times and FICON channel link utilizations vs. MB/sec. The sharp
increase in response times occurs at about 170 MB/sec which is about 85% of the maximum
link capability and indicates that the 2 Gbps link is the limiting resource for this workload.
But processor utilizations are pushed to high levels as well. The 27k read hit benchmark
pushes both processor and link utilizations to high levels with link utilizations slightly higher
than the processor.