<strong>MCP3001</strong>Note: Unless otherwise indicated, V DD = V REF = 5V, f SAMPLE = 200 ksps, f CLK = 14*Sample Rate,T A = 25°CIDDS (pA)60VREF = CS = VDD50403020<strong>10</strong>02.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0V DD (V)Analog Input Leakage (nA)2.01.8 V DD = V REF = 5V1.61.41.21.00.80.60.40.20.0-50 -25 0 25 50 75 <strong>10</strong>0Temperature (°C)FIGURE 2-37: I DDS vs. V DD .FIGURE 2-39: Analog Input Leakage Current vs.Temperature.<strong>10</strong>0.00V DD = V REF = CS = 5V<strong>10</strong>.00IDDS (nA)1.000.<strong>10</strong>0.01-50 -25 0 25 50 75 <strong>10</strong>0Temperature (°C)FIGURE 2-38: I DDS vs. Temperature.DS21293C-page 12© 2007 <strong>Microchip</strong> Technology Inc.
<strong>MCP3001</strong>3.0 PIN DESCRIPTIONS3.1 IN+Positive analog input. This input can vary from IN- toV REF + IN-.3.2 IN-Negative analog input. This input can vary ±<strong>10</strong>0 mVfrom V SS .3.3 CS/SHDN(Chip Select/Shutdown)The CS/SHDN pin is used to initiate communication<strong>with</strong> the device when pulled low and will end a conversionand put the device in low power standby whenpulled high. The CS/SHDN pin must be pulled highbetween conversions.3.4 CLK (<strong>Serial</strong> Clock)The <strong>SPI</strong> clock pin is used to initiate a conversion and toclock out each bit of the conversion as it takes place.See Section 6.2 for constraints on clock speed.3.5 DOUT (<strong>Serial</strong> Data output)The <strong>SPI</strong> serial data output pin is used to shift out theresults of the A/D conversion. Data will always changeon the falling edge of each clock as the conversiontakes place.4.0 DEVICE OPERATIONThe <strong>MCP3001</strong> A/D converter employs a conventionalSAR architecture. With this architecture, a sample isacquired on an internal sample/hold capacitor for1.5 clock cycles starting on the first rising edge of theserial clock after CS has been pulled low. Following thissample time, the input switch of the converter opensand the device uses the collected charge on the internalsample and hold capacitor to produce a serial <strong>10</strong>-bitdigital output code. Conversion rates of 200 ksps arepossible on the <strong>MCP3001</strong>. See Section 6.2 for informationon minimum clock rates. Communication <strong>with</strong> thedevice is done using a 3-wire <strong>SPI</strong>-compatible interface.In this diagram, it is shown that the source impedance(R S ) adds to the internal sampling switch, (R SS ) impedance,directly affecting the time that is required tocharge the capacitor, C SAMPLE . Consequently, a largersource impedance increases the offset, gain, and integrallinearity errors of the conversion.Ideally, the impedance of the signal source should benear zero. This is achievable <strong>with</strong> an operational amplifiersuch as the MCP601, which has a closed loop outputimpedance of tens of ohms. The adverse affects ofhigher source impedances are shown in Figure 4-2.If the voltage level of IN+ is equal to or less than IN-, theresultant code will be 000h. If the voltage at IN+ is equalto or greater than {[V REF + (IN-)] - 1 LSB}, then the outputcode will be 3FFh. If the voltage level at IN- is morethan 1 LSB below V SS , then the voltage level at the IN+input will have to go below V SS to see the 000h outputcode. Conversely, if IN- is more than 1 LSB above Vss,then the 3FFh code will not be seen unless the IN+input level goes above V REF level.4.2 Reference InputThe reference input (V REF ) determines the analog inputvoltage range and the LSB size, as shown below.LSB Size =V REF------------<strong>10</strong>24As the reference input is reduced, the LSB size isreduced accordingly. The theoretical digital output codeproduced by the A/D <strong>Converter</strong> is a function of the analoginput signal and the reference input as shownbelow.<strong>10</strong>24*V INDigital Output Code = -----------------------V REF4.1 Analog InputsThe <strong>MCP3001</strong> provides a single pseudo-differentialinput. The IN+ input can range from IN- to (V REF +IN-).The IN- input is limited to ±<strong>10</strong>0 mV from the V SS rail.The IN- input can be used to cancel small signal common-modenoise which is present on both the IN+ andIN- inputs.For the A/D <strong>Converter</strong> to meet specification, the chargeholding capacitor, C SAMPLE must be given enough timeto acquire a <strong>10</strong>-bit accurate voltage level during the1.5 clock cycle sampling period. The analog inputmodel is shown in Figure 4-1.where:V IN = analog input voltage = V(IN+) - V(IN-)V REF = reference voltageWhen using an external voltage reference device, thesystem designer should always refer to the manufacturer’srecommendations for circuit layout. Any instabilityin the operation of the reference device will have adirect effect on the operation of the ADC.© 2007 <strong>Microchip</strong> Technology Inc. DS21293C-page 13
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