MCP3550/1/3 - Microchip

MCP3550/1/32.0 TYPICAL PERFORMANCE CURVESNote:The graphs and tables provided following this note are a statistical summary based on a limited number ofsamples and are provided for informational purposes only. The performance characteristics listed hereinare not tested or guaranteed. In some graphs or tables, the data presented may be outside the specifiedoperating range (e.g., outside specified power supply range) and therefore outside the warranted range.Note: Unless otherwise specified, T A = +25°C, V DD = 5V, V REF = 2.5V, V SS = 0V, V CM = V REF /2, V IN + = V IN -.All ppm units use 2*V REF as full scale range. Unless otherwise noted, graphs apply to entire MCP3550/1/3 family.INL (ppm)54+125 C32+85 C10-1-40 C-2+25 C-3-4-5-2.5 -1.5 -0.5 0.5 1.5 2.5V IN (V)INL Error (ppm)10864200 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5V REF (V)FIGURE 2-1:(V DD = 2.7V).INL Error vs. Input VoltageFIGURE 2-4:V REF .Maximum INL Error vs.INL (ppm)54+125 C3+85 C210-1- 40 C-2+25 C-3-4-5-2.5 -1.5 -0.5 0.5 1.5 2.5V IN (V)Max INL (ppm)109876543210-50 -25 0 25 50 75 100 125Temperature (°C)FIGURE 2-2:(V DD = 5.0V).INL Error vs. Input VoltageFIGURE 2-5:Temperature.Maximum INL Error vs.INL (ppm)1086420-2-4-6-8-10+125 C+85 C+25 C-40 C-5 -4 -3 -2 -1 0 1 2 3 4 5V IN (V)Output Noise (µV RMS )10987MCP35536543MCP3550/1210-2.5 -1.5 -0.5 0.5 1.5 2.5V IN (Volts)FIGURE 2-3: INL Error vs. Input Voltage(V DD = 5.0V, V REF = 5V).FIGURE 2-6: Output Noise vs. InputVoltage (V DD = 2.7V).© 2009 Microchip Technology Inc. DS21950E-page 7

MCP3550/1/3Note: Unless otherwise specified, T A = +25°C, V DD = 5V, V REF = 2.5V, V SS = 0V, V CM = V REF /2, V IN + = V IN -.All ppm units use 2*V REF as full scale range. Unless otherwise noted, graphs apply to entire MCP3550/1/3 family.Output Noise (µV RMS )1510MCP35535MCP3550/10-2.5 -1.5 -0.5 0.5 1.5 2.5V IN (V)FIGURE 2-7: Output Noise vs. InputVoltage (V DD = 5.0V).Output Noise (µV RMS )10987MCP3553654MCP3550/13210-50 -25 0 25 50 75 100 125Temperature (°C)FIGURE 2-10:Temperature.Output Noise vs.uOutput Noise (µV RMS )10.09.08.07.06.0MCP35535.04.0MCP3550/13.02.01.00.00.0 1.0 2.0 3.0 4.0 5.0V REF (V)Offset (µV)5432102.5 3 3.5 4 4.5 5 5.5V DD (V)FIGURE 2-8: Output Noise vs. V REF .FIGURE 2-11:(V CM =0V).Offset Error vs V DDOutput Noise (µV RMS )10987MCP3553654MCP3550/132102.5 3 3.5 4 4.5 5 5.5V DD (V)FIGURE 2-9: Output Noise vs.V DD .Offset (µV)76543210-50 -25 0 25 50 75 100 125Temperature (°C)FIGURE 2-12: Offset Error vs.Temperature (V REF = 5.0V).DS21950E-page 8© 2009 Microchip Technology Inc.

MCP3550/1/3Note: Unless otherwise specified, T A = +25°C, V DD = 5V, V REF = 2.5V, V SS = 0V, V CM = V REF /2, V IN + = V IN -.All ppm units are ratioed against 2*V REF . Unless otherwise noted, graphs apply to entire MCP3550/1/3 family.Full Scale Error (ppm)5432Positive Full Scale10-1-2Negative Full Scale-3-4-52.5 3 3.5 4 4.5 5 5.5V DD (V)FIGURE 2-13: Full Scale Error vs. V DD .Number of Occurrences4000V DD = 5V3500 V REF = 2.5VV CM = 1.25V3000 V IN = 0VT2500 A = 25C163842000 consecutive readings150010005000-15 -10 -5 0 5 10 15Output Code (LSB)FIGURE 2-16: MCP3550/1 Output NoiseHistogram.Full Scale Error (ppm)10864Positive Full Scale20-2-4-6Negative Full Scale-8-10-50 -25 0 25 50 75 100 125Temperature (°C)FIGURE 2-14:Temperature.Full Scale Error vs.Number of Occurrences180016001400120010008006004002000V DD = 5VV REF = 2.5VV CM = 1.25VV IN = 0VT A = 25°C16384consecutivereadingsFIGURE 2-17:Histogram.-15 -10 -5 0 5 10 15Output Code (LSB)MCP3553 Output NoiseFull Scale Error (ppm)1086420-2-4-6-8-10Positive Full ScaleNegative Full Scale-50 -25 0 25 50 75 100 125Temperature (°C)FIGURE 2-15: Full Scale Error vs.Temperature (V REF = 5.0V).TUE (ppm)5.04.03.02.01.00.0-1.0-2.0-3.0-4.0-5.0-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5V IN (V)FIGURE 2-18: Total Unadjusted Error(TUE) vs. Input Voltage (V DD = 2.7V).© 2009 Microchip Technology Inc. DS21950E-page 9

MCP3550/1/3Note: Unless otherwise specified, T A = +25°C, V DD = 5V, V REF = 2.5V, V SS = 0V, V CM = V REF /2, V IN + = V IN -.All ppm units use 2*V REF as full scale range. Unless otherwise noted, graphs apply to entire MCP3550/1/3 family.TUE (ppm)543210-1-2-3-4-5-2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5V IN (V)Maximum TUE (ppm)6543210-50 -25 0 25 50 75 100 125Temperature (°C)FIGURE 2-19: Total Unadjusted Error(TUE) vs. Input Voltage.FIGURE 2-22:Temperature.Maximum TUE vs.TUE (ppm)1086420-2-4-6-8-10-5 -4 -3 -2 -1 0 1 2 3 4 5V IN (V)FIGURE 2-20: Total Unadjusted Error(TUE) vs. Input Voltage (V REF = 5.0V).TUE (ppm)54.543.532.521.510.502.5 2.7 3 3.3 4 5 5.5V DD (V)FIGURE 2-23: Maximum TUE vs. V DD .Maximum TUE (ppm)1098765432100 1 2 3 4 5V REF (V)FIGURE 2-21: Maximum TUE vs. V REF .I DDS (µA)0.60.50.4MCP3550/10.3MCP35530.20.10-0.1-50 -25 0 25 50 75 100 125Temperature (°C)FIGURE 2-24: I DDS vs. Temperature.DS21950E-page 10© 2009 Microchip Technology Inc.

MCP3550/1/3Note: Unless otherwise specified, T A = +25°C, V DD = 5V, V REF = 2.5V, V SS = 0V, V CM = V REF /2, V IN + = V IN -.All ppm units use 2*V REF as full scale range. Unless otherwise noted, graphs apply to entire MCP3550/1/3 family.I DD (µA)200180160140120100806040200MCP3550-60, MCP3553MCP3550-50, MCP3550/1I DD (µA)160140120100806040200MCP3550-60, MCP3553MCP3550-50, MCP3550/12.5 3 3.5 4 4.5 5 5.5-50 -25 0 25 50 75 100 125V DD (V)Temperature (°C)FIGURE 2-25: I DD vs. V DD . FIGURE 2-26: I DD vs. Temperature.© 2009 Microchip Technology Inc. DS21950E-page 11

MCP3550/1/3NOTES:DS21950E-page 12© 2009 Microchip Technology Inc.

MCP3550/1/33.0 PIN DESCRIPTIONSThe descriptions of the pins are listed in Table 3-1.TABLE 3-1: PIN FUNCTION TABLEMCP3550/1/3Symbol I/O/P DescriptionMSOP, SOIC1 V REF I Reference Voltage Analog Input Pin2 V IN + I Non-inverting Analog Input Pin3 V IN - I Inverting Analog Input Pin4 V SS P Ground Pin5 SCK I Serial Clock Digital Input Pin6 SDO/RDY O Data/Ready Digital Output Pin7 CS I Chip Select Digital Input Pin8 V DD P Positive Supply Voltage PinType Identification: I = Input; O = Output; P = Power3.1 Voltage Reference (V REF )The MCP3550/1/3 devices accept single-endedreference voltages from 0.1V to V DD . Since theconverter output noise is dominated by thermal noise,which is independent of the reference voltage, theoutput noise is not significantly improved bydiminishing the reference voltage at the V REF input pin.A reduced voltage reference will significantly improvethe INL performance (see Figure 2-4); the INL maxerror is proportional to V REF 2 .3.2 Analog Inputs (V IN +, V IN -)The MCP3550/1/3 devices accept a fully differentialanalog input voltage to be connected on the V IN + andV IN - input pins. The differential voltage that isconverted is defined by V IN = V IN + – V IN -. Thedifferential voltage range specified for ensuredaccuracy is from -V REF to +V REF . However, theconverter will still output valid and usable codes withthe inputs overranged by up to 12% (see Section 5.0“Serial Interface”) at room temperature. Thisoverrange is clearly specified by two overload bits inthe output code.The absolute voltage range on these input pins extendsfrom V SS – 0.3V to V DD + 0.3V. Any voltage above orbelow this range will create leakage currents throughthe Electrostatic Discharge (ESD) diodes. This currentwill increase exponentially, degrading the accuracy andnoise performance of the device. The common mode ofthe analog inputs should be chosen such that both thedifferential analog input range and the absolute voltagerange on each pin are within the specified operatingrange defined in Section 1.0 “ElectricalCharacteristics”.3.3 Supply Voltage (V DD , V SS )V DD is the power supply pin for the analog and digitalcircuitry within the MCP3550/1/3. This pin requires anappropriate bypass capacitor of 0.1 µF. The voltage onthis pin should be maintained in the 2.7V to 5.5V rangefor specified operation. V SS is the ground pin and thecurrent return path for both analog and digital circuitryof the MCP3550/1/3. If an analog ground plane isavailable, it is recommended that this device be tied tothe analog ground plane of the Printed Circuit Board(PCB).3.4 Serial Clock (SCK)SCK synchronizes data communication with thedevice. The device operates in both SPI mode 1,1 andSPI mode 0,0. Data is shifted out of the device on thefalling edge of SCK. Data is latched in on the risingedge of SCK. During CS high times, the SCK pin canidle either high or low.3.5 Data Output (SDO/RDY)SDO/RDY is the output data pin for the device. Once aconversion is complete, this pin will go active-low,acting as a ready flag. Subsequent falling clock edgeswill then place the 24-bit data word (two overflow bitsand 22 bits of data, see Section 5.0 “SerialInterface”) on the SPI bus through the SDO pin. Datais clocked out on the falling edge of SCK.© 2009 Microchip Technology Inc. DS21950E-page 13

MCP3550/1/33.6 Chip Select (CS)CS gates all communication to the device and can beused to select multiple devices that share the sameSCK and SDO/RDY pins. This pin is also used tocontrol the internal conversions, which begin on thefalling edge of CS. Raising CS before the first internalconversion is complete places the device in SingleConversion mode. Leaving CS low will place thedevice in Continuous Conversion mode (i.e., additionalinternal conversions will automatically occur). CS maybe tied permanently low for two-wire ContinuousConversion mode operation. SDO/RDY enters a highimpedancestate with CS high.DS21950E-page 14© 2009 Microchip Technology Inc.

MCP3550/1/34.0 DEVICE OVERVIEWThe MCP3550/1/3 devices are 22-bit delta-sigmaADCs that include fully differential analog inputs, athird-order delta-sigma modulator, a fourth-ordermodified SINC decimation filter, an on-chip, low-noiseinternal oscillator, a power supply monitoring circuit andan SPI 3-wire digital interface. These devices can beeasily used to measure low-frequency, low-levelsignals such as those found in pressure transducers,temperature, strain gauge, industrial control or processcontrol applications. The power supply range for thisproduct family is 2.7V to 5.5V; the temperature range is-40°C to +125°C. The functional block diagram for theMCP3550/1/3 devices is shown in Figure 4-1.A Power-On Reset (POR) monitoring circuit is includedto ensure proper power supply voltages during theconversion process. The clock source for the part isinternally generated to ±0.5% over the full-powersupply voltage range and industrial temperature range.This stable clock source allows for superior conversionrepeatability and minimal drift across conversions.The MCP3550/1/3 devices employ a delta-sigmaconversion technique to realize up to 22 bits of nomissing code performance with 21.9 Effective Numberof Bits (ENOB). These devices provide single-cycleconversions with no digital filter settling time. Everyconversion includes an internal offset and gain autocalibrationto reduce device error. These calibrationsare transparent to the user and are done in real-timeduring the conversion. Therefore, these devices do notrequire any additional time or conversion to proceed,allowing easy usage of the devices for multiplexedapplications. The MCP3550/1/3 devices incorporate afourth-order digital decimation filter in order to allowsuperior averaging performance, as well as excellentline frequency rejection capabilities. The oversamplingfrequency also reduces any external anti-aliasing filterrequirements.The MCP3550/1/3 devices communicate with a simple3-wire SPI interface. The interface controls theconversion start event, with an added feature of anauto-conversion at system power-up by tying the CSpin to logic-low. The device can communicate with busspeeds of up to 5 MHz, with 50 pF capacitive loading.The interface offers two conversion modes: SingleConversion mode for multiplexed applications and aContinuous Conversion mode for multiple conversionsin series. Every conversion is independent of eachother. That is, all internal registers are flushed betweenconversions. When the device is not converting, it automaticallygoes into Shutdown mode and, while in thismode, consumes less than 1 µA.ReferenceInputDifferentialAnalog InputGain andOffsetCalibrationChargeTransferThird-OrderΔΣModulatorBitStreamDigitalDecimationFilter (SINC 4 )ConversionCodeSPI 3-wireInterfaceOutputCodeClockInternalOscillatorFIGURE 4-1:MCP3550/1/3 Functional Block Diagram.© 2009 Microchip Technology Inc. DS21950E-page 15

MCP3550/1/34.1 MCP3550/1/3 Delta-SigmaModulator with Internal Offset andGain CalibrationThe converter core of the MCP3550/1/3 devices is athird-order delta-sigma modulator with automatic gainand offset error calibrations. The modulator uses a 1-bitDAC structure. The delta-sigma modulator processesthe sampled charges through switched capacitorstructures controlled by a very low drift oscillator forreduced clock jitter.During the conversion process, the modulator outputsa bit stream with the bit frequency equivalent to thef OSC /4 (see Table 4-1). The high oversamplingimplemented in the modulator ensures very highresolution and high averaging factor to achieve lownoisespecifications. The bit stream output of themodulator is then processed by the digital decimationfilter in order to provide a 22-bit output code at a datarate of 12.5 Hz for the MCP3550-50, 15 Hz for theMCP3550-60, 13.75 Hz for the MCP3551 and 60 Hzfor the MCP3553. Since the oversampling ratio is lowerwith the MCP3553 device, a much higher output datarate is achieved while still achieving 20 bits No MissingCodes (NMC) and 20.6 ENOB.A self-calibration of offset and gain occurs at the onsetof every conversion. The conversion data available atthe output of the device is always calibrated for offsetand gain through this process. This offset and gainauto-calibration is performed internally and has noimpact on the speed of the converter since the offsetand gain errors are calibrated in real-time during theconversion. The real-time offset and gain calibrationschemes do not affect the conversion process.4.2 Digital FilterThe MCP3550/1/3 devices include a digital decimationfilter, which is a fourth-order modified SINC filter. Thisfilter averages the incoming bit stream from themodulator and outputs a 22-bit conversion word inbinary two's complement. When all bits have beenprocessed by the filter, the output code is ready for SPIcommunication, the RDY flag is set on the SDO/RDYpin and all the internal registers are reset in order toprocess the next conversion.Like the commonly used SINC filter, the modified SINCfilter in the MCP3550/1/3 family has the main notchfrequency located at f S /(OSR*L), where f S is the bitstream sample frequency. OSR is the OversamplingRatio and L is the order of the filter.The MCP3550-50 device has the main filter notchlocated at 50 Hz. For the MCP3550-60 device, thenotch is located at 60 Hz. The MCP3551 device has itsnotch located at 55 Hz, and for the MCP3553 device,the main notch is located at 240 Hz, with an OSR of128. (see Table 4-1 for rejection performance).The digital decimation SINC filter has been modified inorder to offer staggered zeros in its transfer function.This modification is intended to widen the main notch inorder to be less sensitive to oscillator deviation or linefrequencydrift. The MCP3551 filter has staggeredzeros spread in order to reject both 50 Hz and 60 Hzline frequencies simultaneously (see Figure 4-2).TABLE 4-1: DATA RATE, OUTPUT NOISE AND DIGITAL FILTER SPECIFICATIONS BY DEVICEDeviceOutput DataRate (t CONV )(Note)OutputNoise(µV RMS )PrimaryNotch(Hz)SampleFrequency(f S )InternalClockf OSC50/60 Hz RejectionMCP3550-50 80.00 ms 2.5 50 25600 Hz 102.4 kHz -120 dB min. at50 HzMCP3550-60 66.67 ms 2.5 60 30720 Hz 122.88 kHz -120 dB min. at60 HzMCP3551 72.73 ms 2.5 55 28160 Hz 112.64 kHz -82 dB min. from48 Hz to 63 Hz. -82 dB at 50 Hz and-88 dB at 60 HzMCP3553 16.67 ms 6 240 30720 Hz 122.88 kHz Not ApplicableNote: For the first conversion after exiting Shutdown, t CONV must include an additional 144 f OSC periods beforethe conversion is complete and the RDY (Ready) flag appears on SDO/RDY.DS21950E-page 16© 2009 Microchip Technology Inc.

MCP3550/1/3:FIGURE 4-2: SINC Filter Response,MCP3550-50 Device.:FIGURE 4-3: SINC Filter Response,MCP3550-60 Device.:Attenuation (dB)Attenuation (dB)Attenuation (dB)0-20-40-60-80-100-1200 50 100 150 200Frequency (Hz)0-20-40-60-80-100-1200 60 120 180 240Frequency (Hz)0-10-20-30-40-50-60-70-80-90-100-110-1200 10 20 30 40 50 60 70 80 90 100 110Frequency (Hz)FIGURE 4-4: SINC Filter Response,MCP3551 Device, Simultaneous 50/60 HzRejection.Normal Mode Rejection (dB)0-20-40-60-80-100-120-1400 28160 56320 84480 112640 140800 168960 197120 225280 253440Frequency (Hz)FIGURE 4-5: SINC Filter Response atInteger Multiples of the Sampling Frequency (f s ).4.3 Internal OscillatorThe MCP3550/1/3 devices include a highly stable andaccurate internal oscillator that provides clock signalsto the delta-sigma ADC with minimum jitter. Theoscillator is a specialized structure with a lowtemperature coefficient across the full range ofspecified operation. See Table 4-1 for oscillatorfrequencies.The conversion time is an integer multiple of theinternal clock period and, therefore, has the sameaccuracy as the internal clock frequency. The internaloscillator frequency is 102.4 kHz ±1% for theMCP3550-50, 112.64 kHz ±1% for the MCP3551, and122.88 kHz ±1% for the MCP3550-60 and MCP3553devices, across the full power supply voltage andspecified temperature ranges.The notch of the digital filter is proportional to theinternal oscillator frequency, with the exact notchfrequency equivalent to the oscillator accuracy(< 1% deviation). This high accuracy, combined withwide notches, will ensure that the MCP3551 will havesimultaneous 50 Hz and 60 Hz line frequency rejectionand the MCP3550-50 or MCP3550-60 devices willhave greater than 120 dB rejection (at either 50 or60 Hz) by the digital filtering, even when jitter ispresent.The internal oscillator is held in the reset conditionwhen the part is in Shutdown mode to ensure very lowpower consumption (< 1 µA in Shutdown mode). Theinternal oscillator is independent of all serial digitalinterface edges (i.e., state machine processing thedigital SPI interface is asynchronous with respect to theinternal clock edges).© 2009 Microchip Technology Inc. DS21950E-page 17

MCP3550/1/34.4 Differential Analog InputsThe MCP3550/1/3 devices accept a fully differentialanalog input voltage to be connected to the V IN+ andV IN- input pins. The differential voltage that is convertedis defined by V IN = V IN + – V IN -. The differential voltagerange specified for ensured accuracy is from -V REF to+V REF .The converter will output valid and usable codes from-112% to 112% of output range (see Section 5.0“Serial Interface”) at room temperature. The ±12%overrange is clearly specified by two overload bits inthe output code: OVH and OVL. This feature allows forsystem calibration of a positive gain error.The absolute voltage range on these input pins extendsfrom V SS - 0.3V to V DD + 0.3V. If the input voltages areabove or below this range, the leakage currents of theESD diodes will increase exponentially, degrading theaccuracy and noise performance of the converter. Thecommon mode of the analog inputs should be chosensuch that both the differential analog input range andabsolute voltage range on each pin are within thespecified operating range defined in Section 1.0“Electrical Characteristics”.Both the analog differential inputs and the referenceinput have switched-capacitor input structures. Theinput capacitors are charged and dischargedalternatively with the input and the reference in order toprocess a conversion. The charge and discharge of theinput capacitors create dynamic input currents at theV IN + and V IN - input pins inversely proportional to thesampling capacitor. This current is a function of thedifferential input voltages and their respective commonmodes. The typical value of the differential inputimpedance is 2.4 MΩ, with V CM = 2.5V, V DD = V REF =5V. The DC leakage current caused by the ESD inputdiodes, even though on the order of 1 nA, can causeadditional offset errors proportional to the sourceresistance at the V IN + and V IN - input pins.From a transient response standpoint and as a firstorderapproximation, these input structures form asimple RC filtering circuit with the source impedance inseries with the R ON (switched resistance when closed)of the input switch and the sampling capacitor. In orderto ensure the accuracy of the sampled charge, propersettling time of the input circuit has to be considered.Slow settling of the input circuit will create additionalgain error. As a rule of thumb, in order to obtain 1 ppmabsolute measurement accuracy, the sampling periodmust be 14 times greater than the input circuit RC timeconstant.4.5 Voltage Reference Input PinThe MCP3550/1/3 devices accept a single-endedexternal reference voltage, to be connected on theV REF input pin. Internally, the reference voltage for theADC is a differential voltage with the non-inverting inputconnected to the V REF pin and the inverting inputconnected to the V SS pin. The value of the referencevoltage is V REF - V SS and the common mode of thereference is always (V REF - V SS )/2.The MCP3550/1/3 devices accept a single-endedreference voltage from 0.1V to V DD. The converteroutput noise is dominated by thermal noise that isindependent of the reference voltage. Therefore, theoutput noise is not significantly improved by loweringthe reference voltage at the V REF input pin. However, areduced reference voltage will significantly improve theINL performance since the INL max error is2proportional to V REF (see Figure 2-4).The charge and discharge of the input capacitor createdynamic input currents at the V REF input pin inverselyproportional to the sampling capacitor, which is a functionof the input reference voltage. The typical value ofthe single-ended input impedance is 2.4 MΩ, withV DD =V REF = 5V. The DC leakage current caused bythe ESD input diodes, though on the order of 1 nAtypically, can cause additional gain error proportional tothe source resistance at the V REF pin.4.6 Power-On Reset (POR)The MCP3550/1/3 devices contain an internal Power-On Reset (POR) circuit that monitors power supplyvoltage V DD during operation. This circuit ensurescorrect device start-up at system power-up and powerdownevents. The POR has built-in hysteresis and atimer to give a high degree of immunity to potentialripple and noise on the power supplies, as well as toallow proper settling of the power supply during powerup.A 0.1 µF decoupling capacitor should be mountedas close as possible to the V DD pin, providing additionaltransient immunity.The threshold voltage is set at 2.2V, with a tolerance ofapproximately ±5%. If the supply voltage falls belowthis threshold, the MCP3550/1/3 devices will be held ina reset condition or in Shutdown mode. When the partis in Shutdown mode, the power consumption is lessthan 1 µA. The typical hysteresis value is around200 mV in order to prevent reset during brown-out orother glitches on the power supply.DS21950E-page 18© 2009 Microchip Technology Inc.

MCP3550/1/3Once a power-up event has occurred, the device mustrequire additional time before a conversion can takeplace. During this time, all internal analog circuitry mustsettle before the first conversion can occur. An internaltimer counts 32 internal clock periods before theinternal oscillator can provide clock to the conversionprocess. This allows all internal analog circuitry tosettle to their proper operating point. This timing istypically less than 300 µs, which is negligible comparedto one conversion time (e.g. 72.7 ms for theMCP3551). Figure 4-6 illustrates the conditions for apower-up and power-down event under typical start-upconditions.4.8 Sleep ModeDuring Sleep mode, the device is not converting and isawaiting data retrieval; the internal analog circuitry isstill running and the device typically consumes 10 µA.In order to restart a conversion while in Sleep mode,toggling CS to a logic-high (placing the part in Shutdownmode) and then back to a logic-low will restart theconversion. Sleep can only be entered in SingleConversion mode. Once a conversion is complete inSingle Conversion mode, the device automaticallyenters Sleep mode.V DD2.2V2.0V300 µs0VResetStart-upNormalOperationResetTimeFIGURE 4-6:Power-On Reset Operation.4.7 Shutdown ModeWhen not internally converting, the two modes ofoperation for the MCP3550/1/3 devices are theShutdown and Sleep modes. During Shutdown mode,all internal analog circuitry, including the POR, is turnedoff and the device consumes less than 1 µA. Whenexiting Shutdown mode, the device must requireadditional time before a conversion can take place.During this time, all internal analog circuitry must settlebefore the first conversion can occur. An internal timercounts 32 internal clock periods before the internaloscillator can provide clock to the conversion process.This allows all internal analog circuitry to settle to theirproper operating point. This timing is typically less than300 µs, which is negligible compared to one conversiontime (72.7 ms for MCP3551).© 2009 Microchip Technology Inc. DS21950E-page 19

MCP3550/1/3NOTES:DS21950E-page 20© 2009 Microchip Technology Inc.

MCP3550/1/35.0 SERIAL INTERFACE5.1 OverviewSerial communication between the microcontroller andthe MCP3550/1/3 devices is achieved using CS, SCKand SDO/RDY. There are two modes of operation:Single Conversion and Continuous Conversion. CScontrols the conversion start. There are 24 bits in thedata word: 22 bits of conversion data and two overflowbits. The conversion process takes place via theinternal oscillator and the status of this conversionmust be detected. The typical method ofcommunication is shown in Figure 5-1. The status ofthe internal conversion is the SDO/RDY pin and isavailable with CS low. A High state on SDO/RDYmeans the device is busy converting, while a Lowstate means the conversion is finished and data isready for transfer using SCK. SDO/RDY remains in ahigh-impedance state when CS is held high. CS mustbe low when clocking out the data using SCK andSDO/RDY.Bit 22 is Overflow High (OVH) when V IN > V REF – 1 LSB,OVH toggles to logic ‘1’, detecting an overflow high inthe analog input voltage.Bit 23 is Overflow Low (OVL) when V IN < -V REF , OVLtoggles to logic ‘1’, detecting an overflow low in theanalog input voltage. The state OVH = OVL = ‘1’ is notdefined and should be considered as an interrupt forthe SPI interface meaning erroneous communication.Bit 21 to bit 0 represents the output code in 22-bitbinary two's complement. Bit 21 is the sign bit and islogic ‘0’ when the differential analog input is positiveand logic ‘1’ when the differential analog input isnegative. From Bit 20 to bit 0, the output code is givenMSb first (MSb is bit 20 and LSB is Bit 0). When theanalog input value is comprised between -V REF andV REF – 1 LSB, the two overflow bits are set to logic ‘0’.The relationship between input voltage and outputcode is shown in Figure 5-1.The delta-sigma modulator saturation point for thedifferential analog input is located at around ±112% ofV REF (at room temperature), meaning that themodulator will still give accurate output codes with anoverrange of 12% below or above the referencevoltage. Unlike the usual 22-bit device, the 22-bit outputcode will not lock at 0x1FFFFF for positive signinputs or 0x200000 for negative sign inputs in order totake advantage of the overrange capabilities of thedevice. This can be practical for closed-loopoperations, for instance. In case of an overflow, theoutput code becomes a 23-bit two's complement outputcode, where the sign bit will be the OVL bit. If anoverflow high or low is detected, OVL (bit 23) becomesthe sign bit (instead of bit 21), the MSb is then bit 21and the converter can be used as a 23-bit two'scomplement code converter, with output code from bitsB21 to B0, and OVL as the sign bit. Figure 5-1summarizes the output coding data format with orwithout overflow high and low.CSSCKSDO/RDYREADYD O O 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R L HHI-ZFIGURE 5-1: Typical Serial Device Communication and Example Digital Output Codes for SpecificAnalog Input Voltages.© 2009 Microchip Technology Inc. DS21950E-page 21

MCP3550/1/35.2 Controlling Internal Conversionsand the Internal OscillatorDuring Shutdown mode, on the falling edge of CS, theconversion process begins. During this process, theinternal oscillator clocks the delta-sigma modulator andthe SINC filter until a conversion is complete. Thisconversion time is t CONV and the timing is shown inFigure 5-2. At the end of t CONV , the digital filter hassettled completely and there is no latency involved withthe digital SINC filter of the MCP3550/1/3.The two modes of conversion for the MCP3550/1/3devices are Single Conversion and ContinuousConversion. In Single Conversion mode, a consecutiveconversion will not automatically begin. Instead, after asingle conversion is complete and the SINC filter havesettled, the device puts the data into the output registerand enters shutdown.In Continuous Conversion mode, a consecutiveconversion will be automatic. In this mode, the deviceis continuously converting, independent of the serialinterface. The most recent conversion data will alwaysbe available in the Output register.When the device exits Shutdown, there is an internalpower-up delay that must be observed.CSInt. Osct CONV Sleep ShutdownSCK (opt)x24SDO/RDYHi-ZHi-ZFIGURE 5-2:Single Conversion Mode.CSInt. OscShutdownt CONVt CONVt CONVSCK (opt)x24SDO/RDYHi-ZFIGURE 5-3: Continuous Conversion Mode.DS21950E-page 22© 2009 Microchip Technology Inc.

MCP3550/1/35.3 Single Conversion ModeIf a rising edge of Chip Select (CS) occurs during t CONV ,a subsequent conversion will not take place and thedevice will enter low-power Shutdown mode aftert CONV completes. This is referred to as SingleConversion mode. This operation is demonstrated inFigure 5-2. Note that a falling edge of CS during thesame conversion that detected a rising edge, as inFigure 5-2, will not initiate a new conversion. The datamust be read during sleep mode, with CSN low, and willbe lost as soon as the part enters in shutdown mode(with a rising edge of CSN). After the final data bit hasbeen clocked out on the 25th clock, the SDO/RDY pinwill go active-high.5.3.1 READY FUNCTION OF SDO/RDYPIN, SINGLE CONVERSION MODEAt every falling edge of CS during the internalconversion, the state of the internal conversion islatched on the SDO/RDY pin to give ready or busyinformation. A High state means the device is currentlyperforming an internal conversion and data cannot beclocked out. A Low state means the device has finishedits conversion and the data is ready for retrieval on thefalling edge of SCK. This operation is demonstrated inFigure 5-4. Note that the device has been put intoSingle Conversion mode with the first rising edge ofCS.Note:CSInt. OscThe Ready state is latched on each fallingedge of CS and will not dynamicallyupdate if CS is held low. CS must betoggled high through low.t CONV5.4 Continuous Conversion ModeIf no rising edge of CS occurs during any givenconversion per Figure 5-3, a subsequent conversionwill take place and the contents of the previous conversionwill be overwritten. This operation is demonstratedin Figure 5-5. Once conversion output data has startedto be clocked out, the output buffer is not refreshed untilall 24 bits have been clocked. A complete read mustoccur in order to read the next conversion in this mode.The subsequent conversion data to be read will then bethe most recent conversion. The conversion time isfixed and cannot be shortened by the rising edge of CS.This rising edge will place the part in Shutdown modeand all conversion data will be lost.The transfer of data from the SINC filter to the outputbuffer is demonstrated in Figure 5-5. If the previousconversion data is not clocked out of the device, it willbe lost and replaced by the new conversion. When thedevice is in Continuous Conversion mode, the mostrecent conversion data is always present at the outputregister for data retrieval.CSInt. Osct CONVSCK & SDO/RDYt CONVtCONVA B CConversion B data is clockedout of the device here.FIGURE 5-5: Most Current ContinuousConversion Mode Data.If a conversion is in process, it cannot be terminatedwith the rising edge of CS. SDO/RDY must firsttransition to a Low state, which will indicate the end ofconversion.SDO/RDYFIGURE 5-4:Conversion Mode.Hi-ZRDY Functionality in Single© 2009 Microchip Technology Inc. DS21950E-page 23

MCP3550/1/35.4.1 READY FUNCTION OF SDO/RDYPIN IN CONTINUOUS CONVERSIONMODEThe device enters Continuous Conversion mode if norising edge of CS is seen during t CONV andconsecutive conversions ensue. SDO/RDY will behigh, indicating that a conversion is in process. Whena conversion is complete, SDO/RDY will change to aLow state. With the Low state of SDO/RDY after thisfirst conversion, the conversion data can be accessedwith the combination of SCK and SDO/RDY. If the dataready event happens during the clocking out of thedata, the data ready bit will be displayed after thecomplete 24-bit word communication (i.e., the dataready event will not interrupt a data transfer).If 24 bits of data are required from this conversion, theymust be accessed during this communication. You canterminate data transition by bringing CS high, but theremaining data will be lost and the converter will go intoShutdown mode. Once the data has been transmittedby the converter, the SDO/RDY pin will remain in theLSB state until the 25th falling edge of SCK. At thispoint, SDO/RDY is released from the Data Acquisitionmode and changed to the RDY state.5.4.2 2-WIRE CONTINUOUSCONVERSION OPERATION,(CS TIED PERMANENTLY LOW)It is possible to use only two wires to communicate withthe MCP3550/1/3 devices. In this state, the device isalways in Continuous Conversion mode, with internalconversions continuously occurring. This mode can beentered by having CS low during power-up or changingit to a low position after power-up. If CS is low at powerup,the first conversion of the converter is initiatedapproximately 300 µs after the power supply hasstabilized.Note:The RDY state is not latched to CS in thismode; the RDY flag dynamically updateson the SDO/RDY pin and remains in thisstate until data is clocked out using theSCK pin.DS21950E-page 24© 2009 Microchip Technology Inc.

MCP3550/1/35.5 Using The MCP3550/1/3 withMicrocontroller (MCU) SPI PortsIt is required that the microcontroller SPI port beconfigured to clock out data on the falling edge of clockand latch data in on the rising edge. Figure 5-6 depictsthe operation shown in SPI mode 1,1, which requiresthat the SCK from the MCU idles in the High state,while Figure 5-7 shows the similar case of SPI Mode0,0, where the clock idles in the Low state. Thewaveforms in the figures are examples of an MCUoperating the SPI port in 8-bit mode, and theMCP3550/1/3 devices do not require data in 8-bitgroups.In SPI mode 1,1, data is read using only 24 clocks orthree byte transfers. The data ready bit must be readby testing the SDO/RDY line prior to a falling edge ofthe clock.In SPI mode 0,0, data is read using 25 clocks or fourbyte transfers. Please note that the data ready bit isincluded in the transfer as the first bit in this mode.CSSCKSDO/RDYD O O 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R H LMCUReceiveBufferOL OH 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Data stored into MCUreceive register aftertransmission of first byteData stored into MCUreceive register aftertransmission of second byteData stored into MCUreceive register aftertransmission of third byteFIGURE 5-6: SPI Communication – Mode 1,1.CSSCKSDO/RDYDR O O 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0H LMCUReceiveBufferDROH OL 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Data stored into MCUreceive register aftertransmission of first byteData stored into MCUreceive register aftertransmission of second byteData stored into MCUreceive register aftertransmission of third byteData stored into MCUreceive register aftertransmission of fourth byteFIGURE 5-7: SPI Communication – Mode 0,0.© 2009 Microchip Technology Inc. DS21950E-page 25

MCP3550/1/3NOTES:DS21950E-page 26© 2009 Microchip Technology Inc.

MCP3550/1/36.0 PACKAGING INFORMATION6.1 Package Marking Information8-Lead MSOPXXXXXXYWWNNNExample:3553E9512568-Lead SOIC (150 mil)Example (MCP3550):XXXXXXXXXXXXYYWWNNN3550-50ESN^^ e3 0951256Example (MCP3551):MCP3551ESN^^ e3 0951256Legend: XX...X Customer-specific informationY Year code (last digit of calendar year)YY Year code (last 2 digits of calendar year)WW Week code (week of January 1 is week ‘01’)NNNe3Alphanumeric traceability codePb-free JEDEC designator for Matte Tin (Sn)* This package is Pb-free. The Pb-free JEDEC designator ( e3 )can be found on the outer packaging for this package.Note:In the event the full Microchip part number cannot be marked on one line, it willbe carried over to the next line, thus limiting the number of availablecharacters for customer-specific information.© 2009 Microchip Technology Inc. DS21950E-page 27

MCP3550/1/3DNE1ENOTE 11 2ebAA2cφA1L1L DS21950E-page 28© 2009 Microchip Technology Inc.

MCP3550/1/3DNeEE1NOTE 11 2 3bhhαAA2φcA1LL1β © 2009 Microchip Technology Inc. DS21950E-page 29

MCP3550/1/3DS21950E-page 30© 2009 Microchip Technology Inc.

MCP3550/1/3APPENDIX A:REVISION HISTORYRevision E (April 2009)The following is the list of modifications:1. Numerous changes made throughout document.Too numerous to itemize.2. DC Characteristics Table, Conversion Times:Changed all minimums from -1.0% to -2.0%.Changed typical for MCP3551 from 72.73 to73.1. Changed all maximums from +1.0% to+2.0%.3. Packaging Outline drawings updated..Revision D (January 2007)The following is the list of modifications:• This update includes revisions to the packagingdiagrams.Revision C (December 2005)The following is the list of modifications:• Added MCP3550-50, MCP3550-60 referencesthroughout this document.Revision B (October 2005)The following is the list of modifications:• Changed LSb refefences to LSB.Revision A (September 2005)• Original Release of this Document.© 2009 Microchip Technology Inc. DS21950E-page 31

MCP3550/1/3NOTES:DS21950E-page 32© 2009 Microchip Technology Inc.

MCP3550/1/3PRODUCT IDENTIFICATION SYSTEMTo order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.PART NO. –X /XXDeviceDevice: MCP3550-50: Single Channel 22-Bit Delta-Sigma ADCMCP3550T-50: Single Channel 22-Bit Delta-Sigma ADC(Tape and Reel)MCP3550-60: Single Channel 22-Bit Delta-Sigma ADCMCP3550T-60: Single Channel 22-Bit Delta-Sigma ADC(Tape and Reel)MCP3551: Single Channel 22-Bit Delta-Sigma ADCMCP3551T: Single Channel 22-Bit Delta-Sigma ADC(Tape and Reel)MCP3553:MCP3553T:TemperatureRangeTemperature Range: E = -40°C to +125°CPackageSingle Channel 22-Bit Delta-Sigma ADCSingle Channel 22-Bit Delta-Sigma ADC(Tape and Reel)Package: MS = Plastic MSOP, 8-leadSN = Plastic SOIC (150 mil Body), 8-leadExamples:a) MCP3550-50E/MS: Extended Temp.,8LD MSOP.b) MCP3550T-50E/MS: Tape and Reel,Extended Temp.,8LD MSOP.c) MCP3550-60E/SN: Extended Temp.,8LD SOIC.d) MCP3550T-60E/SN: Tape and Reel,Extended Temp.,8LD SOIC.a) MCP3551-E/MS: Extended Temp.,8LD MSOP.b) MCP3551T-E/MS: Tape and Reel,Extended Temp.,8LD MSOP.a) MCP3553-E/SN: Extended Temp.,8LD SOIC.b) MCP3553T-E/SN: Tape and Reel,Extended Temp.,8LD SOIC.© 2009 Microchip Technology Inc. DS21950E-page 33

MCP3550/1/3NOTES:DS21950E-page 34© 2009 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:• Microchip products meet the specification contained in their particular Microchip Data Sheet.• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in theintended manner and under normal conditions.• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to ourknowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s DataSheets. Most likely, the person doing so is engaged in theft of intellectual property.• Microchip is willing to work with the customer who is concerned about the integrity of their code.• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does notmean that we are guaranteeing the product as “unbreakable.”Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of ourproducts. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.MICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED, WRITTEN OR ORAL, STATUTORY OROTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY, PERFORMANCE, MERCHANTABILITY ORFITNESS FOR PURPOSE. Microchip disclaims all liabilityarising from this information and its use. Use of Microchipdevices in life support and/or safety applications is entirely atthe buyer’s risk, and the buyer agrees to defend, indemnify andhold harmless Microchip from any and all damages, claims,suits, or expenses resulting from such use. No licenses areconveyed, implicitly or otherwise, under any Microchipintellectual property rights.TrademarksThe Microchip name and logo, the Microchip logo, Accuron,dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,PICSTART, rfPIC, SmartShunt and UNI/O are registeredtrademarks of Microchip Technology Incorporated in theU.S.A. and other countries.FilterLab, Linear Active Thermistor, MXDEV, MXLAB,SEEVAL, SmartSensor and The Embedded Control SolutionsCompany are registered trademarks of Microchip TechnologyIncorporated in the U.S.A.Analog-for-the-Digital Age, Application Maestro, CodeGuard,dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,ECONOMONITOR, FanSense, In-Circuit SerialProgramming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLABCertified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,PICDEM.net, PICtail, PIC 32 logo, PowerCal, PowerInfo,PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, TotalEndurance, WiperLock and ZENA are trademarks ofMicrochip Technology Incorporated in the U.S.A. and othercountries.SQTP is a service mark of Microchip Technology Incorporatedin the U.S.A.All other trademarks mentioned herein are property of theirrespective companies.© 2009, Microchip Technology Incorporated, Printed in theU.S.A., All Rights Reserved.Printed on recycled paper.Microchip received ISO/TS-16949:2002 certification for its worldwideheadquarters, design and wafer fabrication facilities in Chandler andTempe, Arizona; Gresham, Oregon and design centers in Californiaand India. The Company’s quality system processes and proceduresare for its PIC ® MCUs and dsPIC ® DSCs, KEELOQ ® code hoppingdevices, Serial EEPROMs, microperipherals, nonvolatile memory andanalog products. In addition, Microchip’s quality system for the designand manufacture of development systems is ISO 9001:2000 certified.© 2009 Microchip Technology Inc. DS21950E-page 35

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