MCP3550/1/3 - Microchip

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MCP3550/1/34.1 MCP3550/1/3 Delta-SigmaModulator with Internal Offset andGain CalibrationThe converter core of the MCP3550/1/3 devices is athird-order delta-sigma modulator with automatic gainand offset error calibrations. The modulator uses a 1-bitDAC structure. The delta-sigma modulator processesthe sampled charges through switched capacitorstructures controlled by a very low drift oscillator forreduced clock jitter.During the conversion process, the modulator outputsa bit stream with the bit frequency equivalent to thef OSC /4 (see Table 4-1). The high oversamplingimplemented in the modulator ensures very highresolution and high averaging factor to achieve lownoisespecifications. The bit stream output of themodulator is then processed by the digital decimationfilter in order to provide a 22-bit output code at a datarate of 12.5 Hz for the MCP3550-50, 15 Hz for theMCP3550-60, 13.75 Hz for the MCP3551 and 60 Hzfor the MCP3553. Since the oversampling ratio is lowerwith the MCP3553 device, a much higher output datarate is achieved while still achieving 20 bits No MissingCodes (NMC) and 20.6 ENOB.A self-calibration of offset and gain occurs at the onsetof every conversion. The conversion data available atthe output of the device is always calibrated for offsetand gain through this process. This offset and gainauto-calibration is performed internally and has noimpact on the speed of the converter since the offsetand gain errors are calibrated in real-time during theconversion. The real-time offset and gain calibrationschemes do not affect the conversion process.4.2 Digital FilterThe MCP3550/1/3 devices include a digital decimationfilter, which is a fourth-order modified SINC filter. Thisfilter averages the incoming bit stream from themodulator and outputs a 22-bit conversion word inbinary two's complement. When all bits have beenprocessed by the filter, the output code is ready for SPIcommunication, the RDY flag is set on the SDO/RDYpin and all the internal registers are reset in order toprocess the next conversion.Like the commonly used SINC filter, the modified SINCfilter in the MCP3550/1/3 family has the main notchfrequency located at f S /(OSR*L), where f S is the bitstream sample frequency. OSR is the OversamplingRatio and L is the order of the filter.The MCP3550-50 device has the main filter notchlocated at 50 Hz. For the MCP3550-60 device, thenotch is located at 60 Hz. The MCP3551 device has itsnotch located at 55 Hz, and for the MCP3553 device,the main notch is located at 240 Hz, with an OSR of128. (see Table 4-1 for rejection performance).The digital decimation SINC filter has been modified inorder to offer staggered zeros in its transfer function.This modification is intended to widen the main notch inorder to be less sensitive to oscillator deviation or linefrequencydrift. The MCP3551 filter has staggeredzeros spread in order to reject both 50 Hz and 60 Hzline frequencies simultaneously (see Figure 4-2).TABLE 4-1: DATA RATE, OUTPUT NOISE AND DIGITAL FILTER SPECIFICATIONS BY DEVICEDeviceOutput DataRate (t CONV )(Note)OutputNoise(µV RMS )PrimaryNotch(Hz)SampleFrequency(f S )InternalClockf OSC50/60 Hz RejectionMCP3550-50 80.00 ms 2.5 50 25600 Hz 102.4 kHz -120 dB min. at50 HzMCP3550-60 66.67 ms 2.5 60 30720 Hz 122.88 kHz -120 dB min. at60 HzMCP3551 72.73 ms 2.5 55 28160 Hz 112.64 kHz -82 dB min. from48 Hz to 63 Hz. -82 dB at 50 Hz and-88 dB at 60 HzMCP3553 16.67 ms 6 240 30720 Hz 122.88 kHz Not ApplicableNote: For the first conversion after exiting Shutdown, t CONV must include an additional 144 f OSC periods beforethe conversion is complete and the RDY (Ready) flag appears on SDO/RDY.DS21950E-page 16© 2009 Microchip Technology Inc.
MCP3550/1/3:FIGURE 4-2: SINC Filter Response,MCP3550-50 Device.:FIGURE 4-3: SINC Filter Response,MCP3550-60 Device.:Attenuation (dB)Attenuation (dB)Attenuation (dB)0-20-40-60-80-100-1200 50 100 150 200Frequency (Hz)0-20-40-60-80-100-1200 60 120 180 240Frequency (Hz)0-10-20-30-40-50-60-70-80-90-100-110-1200 10 20 30 40 50 60 70 80 90 100 110Frequency (Hz)FIGURE 4-4: SINC Filter Response,MCP3551 Device, Simultaneous 50/60 HzRejection.Normal Mode Rejection (dB)0-20-40-60-80-100-120-1400 28160 56320 84480 112640 140800 168960 197120 225280 253440Frequency (Hz)FIGURE 4-5: SINC Filter Response atInteger Multiples of the Sampling Frequency (f s ).4.3 Internal OscillatorThe MCP3550/1/3 devices include a highly stable andaccurate internal oscillator that provides clock signalsto the delta-sigma ADC with minimum jitter. Theoscillator is a specialized structure with a lowtemperature coefficient across the full range ofspecified operation. See Table 4-1 for oscillatorfrequencies.The conversion time is an integer multiple of theinternal clock period and, therefore, has the sameaccuracy as the internal clock frequency. The internaloscillator frequency is 102.4 kHz ±1% for theMCP3550-50, 112.64 kHz ±1% for the MCP3551, and122.88 kHz ±1% for the MCP3550-60 and MCP3553devices, across the full power supply voltage andspecified temperature ranges.The notch of the digital filter is proportional to theinternal oscillator frequency, with the exact notchfrequency equivalent to the oscillator accuracy(< 1% deviation). This high accuracy, combined withwide notches, will ensure that the MCP3551 will havesimultaneous 50 Hz and 60 Hz line frequency rejectionand the MCP3550-50 or MCP3550-60 devices willhave greater than 120 dB rejection (at either 50 or60 Hz) by the digital filtering, even when jitter ispresent.The internal oscillator is held in the reset conditionwhen the part is in Shutdown mode to ensure very lowpower consumption (< 1 µA in Shutdown mode). Theinternal oscillator is independent of all serial digitalinterface edges (i.e., state machine processing thedigital SPI interface is asynchronous with respect to theinternal clock edges).© 2009 Microchip Technology Inc. DS21950E-page 17
Page 7 and 8: MCP3550/1/32.0 TYPICAL PERFORMANCE
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Page 13 and 14: MCP3550/1/33.0 PIN DESCRIPTIONSThe
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Page 21 and 22: MCP3550/1/35.0 SERIAL INTERFACE5.1
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Page 27 and 28: MCP3550/1/36.0 PACKAGING INFORMATIO
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Page 31 and 32: MCP3550/1/3APPENDIX A:REVISION HIST
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MCP3550/1/3 - Microchip

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