A Delta-Sigma Fractional-N Frequency Synthesizer for Quad ... - JSTS

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268 JAEWOOK SHIN et al : A DELTA-SIGMA FRACTIONAL-N FREQUENCY SYNTHESIZER FOR~AFC6V DDTCXO/RfRf VPFD/CPOff-chipVDD/2LOGEN/2/2/6L1 & L2UHFVHFIIIV REFRegulatingAm plifierR 5C 5M 5L 1C 1ProgrammableDFF Prescaler /2CounterM 3 M 4DSML tankFig. 1. Frequency synthesizer architecture.and multiple standards. Therefore, fractional-N architecturewith a third-order multi-bit delta sigma modulator(DSM) is realized. Fig. 1 shows the PLL architecture.Two VCO’s cover the quad-band; a high-band VCO(VCOH) covering 2900 ~ 3350 MHz and a low-bandVCO (VCOL) covering 940 ~ 1724 MHz. LOGENblock generates LO signals, in which the divide-by-6 isused for the VHF band and the divide-by-2’s are used forL1/L2 and UHF bands. These divider circuits are basedon the current-mode logic (CML) DFF for simple I/Qgeneration. Meanwhile, the divide-by-2 and the 4/5 dualmodulusprescaler in the feedback path are designed byutilizing true-single-phase-clock (TSPC) logic. A DFFafter the programmable counter synchronizes its outputto the prescaler output. This re-timing block significantlyeliminates the accumulated phase noise created by theasynchronous programmable counter. Automatic frequencycontrol (AFC) block is based on the pulse-counting andcomparison method. The number of the pulse-countingand comparison operation is programmable so that thelock time can be optimized. Typical AFC search time forthe 6-bit coarse tuning is less than 150 μsec. A thirdorder loop filter is used, of which only three componentsare implemented off chip.III. BUILDING BLOCK DESIGN3.1 Wideband VCO with Linearized Coarse TuningFig. 2 shows the VCO circuit schematic. A regulatingamplifier is employed to reduce the power supplysensitivity of the VCO and thereby its phase noisecontribution. Reference voltage V REF is generated by areplica circuit with a bandgap reference current. Thesimulated output noise of the bandgap circuit is 12.2 and10.9 nV/√Hz at 100 kHz and 1 MHz, respectively. A lowpass filter of R 5 and C 5 is employed to further suppressthe noise transferred from the regulator.Fig. 2. VCO circuit schematic.Cap. BankM 1 M 2Conventional binary weighted cap bank is utilized forthe VCOH whose fractional bandwidth is about 25 %.However, for the VCOL whose fractional bandwidth isover 70 % considering PVT variations, the conventionalcap bank cannot be used due to the extremely widetuning range. The K VCO and the frequency step per a capbank code vary over 10 times. Such a big K VCO variationmakes difficult optimal design of the PLL loopcharacteristics, possibly leading to severe degradation ofphase noise and lock time in some channels. The bigvariation of the per-code frequency step also prohibitsoptimal design of AFC search time because the numberof pulse-counting must be set unnecessarily high enoughto detect the smallest frequency step. Hauspie et al.proposed a combined tuning technique of capacitor bank,varactor, and active core size to address these problems[7]. However, we found that the method showed verylimited effects for such a wide bandwidth of this workdue to the conventional binary-weighted cap bank structure.Here we propose a novel pseudo-exponential cap bankstructure. Fig. 3 shows the structure. It consists of a subsectioncap bank, a variable-slope linear cap bank, and a varactorbank. Fig. 4 illustrates the effects of the proposed capbank by comparing the coarse tuning characteristics thatcan be obtained by the proposed and the conventionalcap bank structures. Since the VCO output frequency isdetermined by 1/(2π√LC), it would be ideal to make thetotal capacitance of a cap bank vary in an exponentialform of n -2 with respect to the cap bank code n. However,this is not practical for real implementation because of theL 2
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.7, NO.4, DECEMBER, 2007 26955 5CLK432242(a)Fig. 3. Pseudo-exponential capacitor bank structure.CLKD Q D QMCOUTDQ(b)Fig. 5. (a)TSPC divide-by-2 circuit and (b) TSPC 4/5 prescalerlogic diagram.LSB 20A3IN23MSB 33-bitAdd24-bitAdd24-bitReg24-bitAdd24-bitReg24-bitAdd24-bitRegA226-bitAdd3OUTA1(a)Fig. 4. Comparison of coarse tuning characteristics by theconventional binary-weighted cap bank and the proposedpseudo-exponential cap bank structure. (a) Frequency tuningcharacteristics. (b) Frequency and K vco variation against the capbank tuning code at a fixed V tune .20IN20-bitadderError Cancellation Network andMapping LogicC1C220-bitadderC320-bitadder3OUTextremely huge ratio of the maximum and minimumcapacitances (e.g. 64 2 for 6-bit coarse tuning in VCO).Thus, we mimic the n -2 -dependency by using apseudo-exponentially varying capacitance. As shown inFig. 4, the total tuning range is divided into foursubsections (B n ). Within each subsection, capacitancevaries linearly with a different slope. The slope isdetermined by the different unit capacitance whichvaries from 1⋅C unit to 3⋅C unit in each subsection. Duringthe inter-subsection transitions, the cumulative capacitanceis re-adjusted in the subsection cap bank to make the totalcapacitance vary smoothly. Also, the varactor capacitance isadjusted in each subsection by the varactor bank in orderto keep the K VCO constant. This proposed structure isadopted for the wideband VCOL, which is referred to asVCOL-LCT. By using this structure, the coarse tuningcharacteristics are dramatically linearized.CLK20-bitregister20-bitregister(b)20-bitregisterFig. 6. Logic block diagram of designed delta-sigma modulatorswith 20-bit resolution. (a) 3 rd -order 3-bit single-loop CIFF and(b) MASH-111.3.2 Divide-by-2, 4/5-Prescaler, and PFD in TSPC logicThe divide-by-2 and 4/5 dual-modulus prescaler in thefeedback path are realized in the TSPC logic. Fig. 5(a)shows the circuit schematic of the divide-by-2, where theFET widths are shown while the gate length is minimum0.18 μm. The widths are optimized for high speed operationand large swing by trading off the self-capacitance andthe driving capability. The same DFF is also used for thedual-modulus prescaler, whose circuit is shown in Fig.5(b). In the simulation, the maximum operation frequenciesof the divide-by-2 and the prescaler are 6 GHz and 3.5
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