A Delta-Sigma Fractional-N Frequency Synthesizer for Quad ... - JSTS

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270 JAEWOOK SHIN et al : A DELTA-SIGMA FRACTIONAL-N FREQUENCY SYNTHESIZER FOR~GHz in the worst condition, while they goes up to 9 GHzand 4.5 GHz in the typical condition. Moreover, thecurrent consumption of the prescaler is only 0.8 mA. Wehave found that the TSPC logic dramatically reduces thepower consumption and silicon area compared to theconventional CML logic. The TSPC logic DFF is alsoused in the PFD circuit in order to minimize the timingmismatch of the UP/DN pulses.3.3 Delta-Sigma ModulatorIn general, DSM poses significant impacts on thephase noise performance of the PLL. We implement twotypes of DSM: a 3 rd -order 3-bit single-loop DSM ofCIFF (cascaded integrators with distributed feedforward)type which is similar to that in [8] and MASH-111 with20-bit resolution. Fig. 6 shows the block structures ofsingle-loop modulator and MASH-111. In single-loopmodulator, the coefficients A 1 , A 2 , and A 3 are 2, 1.5, and0.5, respectively. Fig. 7 shows the simulated PSDs (powerspectral density) of each modulator. It is clearly seen thatboth are non-tonal. Fig. 8 compares NTFs (noise transferfunction) of MASH-111 and single-loop modulator. Itclearly exhibits the great difference of the NTF’s of thetwo DSMs. According to the linear analysis results, themaximum and integral quantization noises of the implementedsingle-loop architecture are found to be considerably lessthan the conventional MASH-111 structure, only about40 % and 28 %, respectively. Time-domain simulation isalso performed to examine the dynamic range. Fig. 9shows the internal node values in the DSM with respectto the input value. As can be seen, the dynamic range ofMagnitude (dB)0-50-100-150MASHSingleLoop-20010 -3 10 -2 10 -1Normalized Frequency (Hz)Fig. 7. Simulated power spectral density of MASH-111 andsingle-loop delta-sigma modulators.this architecture is about -2.5 ~ +2.0, which is significantlylarger than the conventional MASH-111 whose dynamicrange is only -0.5 ~ +0.5. The time-domain simulationalso shows the number of output levels is only about 4while that of the MASH-111 is 8, possibly leading toless noise folding and lower in-band noise. For theseadvantages, the single-loop CIFF architecture is chosenin this work.IV. MEASUREMENT RESULTSThe frequency synthesizer was fabricated in a 0.18-μm RF CMOS process. Fig. 10 shows the chip micrograph.The die area is 2.5×2.5 mm 2 . It is packaged in a 40-pinleadless plastic chip carrier (LPCC) and tested on anevaluation printed circuit board with a 1.8-V supply. Itdissipates 21 mA for UHF/L1/L2 bands and 23 mA forVHF band. The slight additional currents at VHF band isconsumed by the divider-by-6 in the LOGEN block.|NTF(z)|8642MASHSingleLoop00.0 0.1 0.2 0.3 0.4 0.5Normalized Frequency (Hz)Fig. 8. Noise transfer function of MASH-111 and single-loopdelta-sigma modulators.SL Internal Node Values20151050-5-10-15-20-4 -2 0 2Input ValueFig. 9. Dynamic range simulation of the single-loop delta-sigmamodulator.
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.7, NO.4, DECEMBER, 2007 271Fig. 10. Chip micrograph.Frequency (MHz)19001800170016001500140013001200110010009000.0 0.3 0.6 0.9 1.2 1.5 1.8Tuning Voltage (V)0.0 0.3 0.6 0.9 1.2 1.5 1.8(a)(b)Fig. 12. Measured frequency tuning characteristics of the lowband VCO with (a) the proposed pseudo-exponential cap bankand (b) the conventional binary weighted cap bank.Frequency (MHz)380036003400320030002800180016001400120010008000.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8Tuning Voltage (V)Fig. 11. Measured frequency tuning characteristics of the lowbandand high-band VCO’s.Fig. 11 shows the measured frequency tuning rangesof the VCOH and VCOL-LCT which are 2882 ~ 3775MHz and 924 ~ 1823 MHz, respectively. They successfullycover the target ranges. The measured phase noises are -90 dBc/Hz at 100 kHz offset and -122 dBc/Hz at 1.45MHz offset for the 3 GHz output frequency in theVCOH, and -110 dBc/Hz at 100 kHz offset and -135dBc/Hz at 1.45 MHz offset for the 1-GHz outputfrequency in the VCOL-LCT.In order to examine the effects of the proposed pseudoexponentialcap bank structure, a test VCO with theconventional cap bank structure is also fabricated andcompared. Fig. 12 shows the measured coarse tuningcharacteristics of VCOL and VCOL-LCT. For the VCOL,the ranges of the K VCO and the frequency step are 23 ~123 MHz/V and 5 ~ 29 MHz/code, respectively. For theVCOL-LCT, they are reduced to 37 ~ 72 MHz/V and 9 ~16 MHz/code at V tune = 0.9 V. Thus the variation of(a)(b)Fig. 13. PLL phase noise measurement. (a) Integer-N mode at825.6 MHz. (b) Fractional-N mode at 827.5 MHz.K VCO is reduced from 530 % to 190 % and the variationof the frequency step is reduced from 580 % to 180 %.They correspond to 3.2- and 2.7-times reduction, respectively.Fig. 13 shows the measured phase noise of the PLL. Inthe measurement, the loop bandwidth is 70 kHz, thereference frequency is 19.2 MHz, and the charge pumpcurrent is 2 mA. Fig. 13(a) is for the integer-N modewith the output frequency of 825.6 MHz and Fig. 13(b)is for the fractional-N mode with the output frequency of827.52 MHz where the DSM output value is +0.1. Thein-band noise at 1 kHz is -95 dBc/Hz for the integer-Nmode and becomes -91.2 dBc/Hz for the fractional-Nmode, which is only 3.8-dB degradation. The phasenoises at 100 kHz and 1.45 MHz offsets are -101.7 and -132.9 dBc/Hz for the integer-N mode, and -100.9 and -130.9 dBc/Hz for the fractional-N mode. In the fractional-
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