Chapter 9

Latching of Address Bus Address bus latch ic : 74373; octal latch device During T1 A0 – A19 is latched along with control signal BHE in the address bus latch. A17L – A19L are decoded ( via address decoder 74LS138 ) to produce CE0’ toCE7’ ALE is produced by 8288 buc controller , applied to CLK of 74373 A1L – A16L, CE0’ – CE7’ applied to the memory subsystem A0L applied to Bank Control Logi ( READ , WRITE ) to identify the which banks isbeen accessedBus Control Logic ( Write, Read ) determines which memory bank isaccessed MRDC’ – BCL –Read ( used during Read bus cycle ) MWTC’ - BCL Write ( used during Write bus cycle ) Bus Transeviers control the direction of the data transfer between 8086and memory subsystemDEN from 8288 is applied to EN of Data Bus trans.DT/R’ from 8288 is applied to DIR of Data Bus trans.