Chapter 9

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Memory Capacity and Memory OrganizationK x NAddress[(log 2 (K)-1):0]MEMData[(N-1):0]x2K locations, N bits per location , Address bus has log 2 (K) address lines, data bus has N data lines.Chip capacity : number of bits a memory chipc can store , defined in bits , i.e. 1 Kbits, Mbits,( note : storage capacities of computer : Bytes)•memory chip has 64M : bits Computer has 64M : bytesMemory organization :• Each location can hold 1, 4 or 8 bits ( designed internally ) ; equal to # of data pin• How many location : address pins.2 x +y• referred as organization ; x is the number of address pins , y is number of bits in eachlocation
ExampleEx 1. MC has 12 address pin and 8 data pin, (a) organization ( b) capacityEx.2 A 512 MC has 8 pins for data (a) the organization (b) number of address pinsEx 3. Organization ? Capacity ? Of the following EPROM ?Ex.4 Intel 2716 has organization : 2K X 8. What is its capacity, how many address lines it has
Page 3 and 4: 1 MEMORY CONTROLSIGNALS
Page 5 and 6: Memory Control Signals : Minumim Mo
Page 7 and 8: Memory Control Signals : Maximum Mo
Page 9 and 10: Read and write bus cycle
Page 11 and 12: Write Bus Cycle 8088- minmode
Page 13 and 14: T1 T2 T3 T48086 Write CycleCLK/S0,
Page 15 and 16: 8086 Read Cycle (1 Wait StateT1 T2
Page 17 and 18: 8088 minimum mode MIC block diagram
Page 19: Finally …. ( minimum ) 8086 or 80
Page 22: Address Latch circuit: = 74F3738 in
Page 25 and 26: Address bus with latch and Decoder
Page 27 and 28: Bank Write and Bank Read Control Lo
Page 29 and 30: Data Bus Transceiver Design ( 8086
Page 31 and 32: Note that G input is the control in
Page 33 and 34: 74LS 138 ( address decoder )
Page 35 and 36: 4. . MEMORY SUBSYSTEMSTypes of memo
Page 37 and 38: Primary and Secondary MemoryCompute
Page 39 and 40: Memory Hierarchy
Page 41: Memory DevicesROM MemoryROM permane
Page 45: Memory Connections: diagramAddress[
Page 49 and 50: 1) Address decoding using simple NA
Page 51 and 52: Semiconductor Memory Device Archite
Page 53: Address decoding using simple NAND
Page 56 and 57: Address decoding using a programmab
Page 58: Data integrity How to ensure data r
Page 62 and 63: Design a 1MB memory system consisti
Page 64: Memory Address Decoding Design a 1M

Chapter 9

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