MC95FG0128 - abov.co.kr

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MC95FG0128SUBXIN I Sub Oscillator input -DSDAI/OOCD Data input/outputIf it doesn’t use, it need pull-up resistorInputDSCLIOCD clock inputIf it doesn’t use, it need pull-up resistorInputTEST mode enablenTESTInTEST is the same function like internal PORexcept remaining port configuration settingvalue.InputnTEST needs about 1k pull-up resistor.VDD18PInternal 1.8V VDDVDD18 needs capacitor for VDD1.8 stablevoltage.Power30 Jan 16, 2012 Ver.2.6
MC95FG01286. Port Structures6.1 General Purpose I/O PortLevelShift ( 1.8V to ExtVDD)LevelShift (ExtVDD to 1.8V)PULL-UPREGISTERVDDOPEN DRAINREGISTERVDDVDDDATAREGISTERSUB-FUNC DATA OUTPUT0MUX1PADSUB-FUNC ENABLEDIRECTIONREGISTERSUB-FUNC DIRECTION0MUX1R(400Ω)PORTx INPUTMUX010SUB-FUNCDATA INPUTMUX1QDCPrDEBOUNCECLKCMOS orSchmittLevelInputDEBOUNCEENABLEANALOG CHANNELENABLEANALOG INPUTANALOG INPUT(without Resistor)Figure 6-1 General Purpose I/O PortJan 16, 2012 Ver.2.6 31
Page 1 and 2: MC95FG0128ABOV SEMICONDUCTOR Co., L
Page 3 and 4: MC95FG0128Published by FAE Team2009
Page 5 and 6: MC95FG012810.5 Interrupt Sequence .
Page 8 and 9: MC95FG0128Figure 11-15 PWM Mode ...
Page 10 and 11: MC95FG0128MC95FG01281. OverviewCMOS
Page 12 and 13: MC95FG01281.4 Development Tools1.4.
Page 14 and 15: MC95FG01282. Block DiagramnTESTDSCL
Page 19 and 20: DSDAP20/AN0/AVREFP21/AN1DSCLP22/AN2
Page 24 and 25: MC95FG0128Figure 4-3 80 pin MQFP pa
Page 26 and 27: MC95FG0128Figure 4-5 64 pin LQFP14
Page 28 and 29: MC95FG0128P36 AN8~AN14 can be selec
Page 32 and 33: MC95FG01286.2 External Interrupt I/
Page 34 and 35: MC95FG01287.3 A/D Converter Charact
Page 36 and 37: MC95FG01287.6 Brown Out Detector Ch
Page 38 and 39: MC95FG01287.10 DC CharacteristicsTa
Page 40 and 41: MC95FG01287.12 SPI CharacteristicsT
Page 42 and 43: MC95FG01288. MemoryThe MC95FG0128 a
Page 44 and 45: MC95FG01288.2 Data MemoryFigure 8-2
Page 46 and 47: MC95FG01288.3 EEPROM Data Memory an
Page 48 and 49: MC95FG01288.4.2 Compiler Compatible
Page 50 and 51: MC95FG0128MEX1 (Memory Extension Re
Page 53 and 54: MC95FG0128P6IO C1H R/W 00H P6 Direc
Page 55 and 56: MC95FG0128PxDB (Px Debounce Enable
Page 57 and 58: MC95FG012810.2 External InterruptTh
Page 59 and 60: MC95FG012810.4 Interrupt Vector Tab
Page 61 and 62: MC95FG012810.6 Effective Timing aft
Page 63 and 64: MC95FG012810.8 Interrupt Enable Acc
Page 65 and 66: MC95FG0128priority than high interr
Page 67 and 68: MC95FG0128INT10EINT9EINT8EINT7EINT6
Page 69 and 70: MC95FG01280 Disable1 EnableINT34E R
Page 71 and 72: MC95FG012811. Peripheral Hardware11
Page 73 and 74: MC95FG0128CS[1:0]Note2) if XINENA b
Page 75 and 76: MC95FG012811.2 BIT11.2.1 OverviewTh
Page 77 and 78: MC95FG012811.3 WDT11.3.1 OverviewTh
Page 79 and 80: MC95FG012811.3.6 WDT Interrupt Timi
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MC95FG012811.4.4 Watch Timer Regist
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MC95FG012811.5 Timer/PWM11.5.1 8-bi
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MC95FG0128Match with T0DR/T1DRT0DR/
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MC95FG0128T0CRT0EN T0PE CAP0 T0CK2
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MC95FG012811.5.1.5 16 Bit Capture M
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MC95FG0128Source Clock(f X)T1 00 01
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MC95FG0128T0EN Control Timer 00 Tim
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MC95FG0128T1 (Timer 1 Register: Rea
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MC95FG012811.5.2.3 16-Bit Capture M
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MC95FG0128Source Clock(f X)Tx 00 01
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MC95FG01282F38H7 6 5 4 3 2 1 0TxEN
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MC95FG0128PWM2HDR, PWM3HDR, PWM4HDR
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MC95FG012811.6 Buzzer Driver11.6.1
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MC95FG012811.7 USART11.7.1 Overview
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MC95FG012811.7.3 Clock GenerationUB
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MC95FG012811.7.6 Data formatA seria
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MC95FG012811.7.8.3 Parity Generator
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MC95FG0128RxDIDLESTARTBIT0Sample(U2
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MC95FG0128XCK(UCPOL=0)XCK(UCPOL=1)S
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MC95FG0128UCTRL11 FAH R/W 00H USART
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MC95FG0128TXERXEUSARTENU2X0 Interru
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MC95FG0128Jan 16, 2012 Ver.2.6 123
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MC95FG012811.7.14 Baud Rate setting
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MC95FG012811.8.3 Data Transmit / Re
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MC95FG012811.8.7 SPI Register descr
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MC95FG012811.9 I 2 C11.9.1 Overview
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MC95FG0128PSDAMSBAcknowledgementSig
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MC95FG0128Note that when a I 2 C in
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MC95FG0128The next figure depicts a
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MC95FG0128STOP bit in I2CMR.4) No A
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MC95FG0128The next figure shows flo
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MC95FG0128IDLES or SrSLA+WGCALL0x95
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MC95FG0128I2CSR (I 2 C Status Regis
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MC95FG0128GCALLENThis bit decides w
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MC95FG0128AnalogInputAN0 ~ AN14Anal
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MC95FG012811.10.6 Register descript
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MC95FG012811.11 CALCULATOR_AI11.11.
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MC95FG012811.11.3 Calculator Librar
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MC95FG012812. Power Down Operation1
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MC95FG0128The source for exit from
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MC95FG012812.5.1 Register MapTable
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MC95FG012813.4 RESET Noise Cancelle
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MC95FG0128:VDD Input:Internal OSCRe
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MC95FG012813.7 Brown Out Detector P
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MC95FG0128PORFEXTRFWDTRFOCDRFBODRFB
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MC95FG0128FormatconverterTarget MCU
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MC95FG012814.2.2.2 Bit transferDSDA
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MC95FG012815. Memory Programming15.
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MC95FG0128WRITEREADnFERSTnPBRST0 0
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MC95FG0128Program and erase time is
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MC95FG012811 10 9 8 7 6 5 4 3 2 1 0
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MC95FG0128Master ResetPage Buffer R
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MC95FG0128(Only main cell area is e
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MC95FG0128(1) Write 0xA5 to FEDR.(2
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MC95FG0128Jan 16, 2012 Ver.2.6 189
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MC95FG0128nRD H H H H H H H H H H H
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MC95FG012815.6 Mode entrance method
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MC95FG012816. Configure option16.1
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MC95FG0128XRL A,dir Exclusive-OR di
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MC95FG0128B. Package relationMC95FG
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MC95FG0128 - abov.co.kr

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