MC95FG0128 - abov.co.kr

More documents

Recommendations

Info

MC95FG01288. MemoryThe MC95FG0128 addresses two separate address memory stores: Program memory and Datamemory. The logical separation of Program and Data memory allows Data memory to be assessed by8-bit addresses, which can be more quickly stored and manipulated by 8-bit CPU. Nevertheless, 16-bit Data memory addresses can also be generated through the DPTR register.Program memory can only be read, not written to. There can be up to 64K bytes of Program memoryin a bank. In the MC95FG0128 FLASH version of these devices the 128K bytes of Program memoryare provided on-chip. Data memory can be read and written to up to 256 bytes internal memory(DATA) including the stack area and 8K bytes of external data memory(XRAM).8.1 Program MemoryA 16-bit program counter is capable of addressing up to 64K bytes for one bank of memory space,but this device has 128K bytes program memory space with bank selection scheme.Figure 8-1 shows a map of the lower part of the program memory. After reset, the CPU beginsexecution from location 0000H. Each interrupt is assigned a fixed location in program memory. Theinterrupt causes the CPU to jump to that location, where it commences execution of the serviceroutine. External interrupt 0, for example, is assigned to location 0003H. If external interrupt 0 is goingto be used, its service routine must begin at location 0003H. If the interrupt is not going to be used, itsservice location is available as general purpose program memory. If an interrupt service routine isshort enough (as is often the case in control applications), it can reside entirely within that 8 byteinterval. Longer service routines can use a jump instruction to skip over subsequent interrupt locations,if other interrupts are in use.42 Jan 16, 2012 Ver.2.6
MC95FG0128FFFFH64K BytesTotal128K Bytes64K BytesBank 10000HBank 0Figure 8-1 Program memory- User Function Mode: 128KBytes Included Interrupt Vector Region- Non-volatile and reprogramming memory: Flash memory based on EEPROM cellJan 16, 2012 Ver.2.6 43
Page 1 and 2: MC95FG0128ABOV SEMICONDUCTOR Co., L
Page 3 and 4: MC95FG0128Published by FAE Team2009
Page 5 and 6: MC95FG012810.5 Interrupt Sequence .
Page 8 and 9: MC95FG0128Figure 11-15 PWM Mode ...
Page 10 and 11: MC95FG0128MC95FG01281. OverviewCMOS
Page 12 and 13: MC95FG01281.4 Development Tools1.4.
Page 14 and 15: MC95FG01282. Block DiagramnTESTDSCL
Page 19 and 20: DSDAP20/AN0/AVREFP21/AN1DSCLP22/AN2
Page 24 and 25: MC95FG0128Figure 4-3 80 pin MQFP pa
Page 26 and 27: MC95FG0128Figure 4-5 64 pin LQFP14
Page 28 and 29: MC95FG0128P36 AN8~AN14 can be selec
Page 30 and 31: MC95FG0128SUBXIN I Sub Oscillator i
Page 32 and 33: MC95FG01286.2 External Interrupt I/
Page 34 and 35: MC95FG01287.3 A/D Converter Charact
Page 36 and 37: MC95FG01287.6 Brown Out Detector Ch
Page 38 and 39: MC95FG01287.10 DC CharacteristicsTa
Page 40 and 41: MC95FG01287.12 SPI CharacteristicsT
Page 44 and 45: MC95FG01288.2 Data MemoryFigure 8-2
Page 46 and 47: MC95FG01288.3 EEPROM Data Memory an
Page 48 and 49: MC95FG01288.4.2 Compiler Compatible
Page 50 and 51: MC95FG0128MEX1 (Memory Extension Re
Page 53 and 54: MC95FG0128P6IO C1H R/W 00H P6 Direc
Page 55 and 56: MC95FG0128PxDB (Px Debounce Enable
Page 57 and 58: MC95FG012810.2 External InterruptTh
Page 59 and 60: MC95FG012810.4 Interrupt Vector Tab
Page 61 and 62: MC95FG012810.6 Effective Timing aft
Page 63 and 64: MC95FG012810.8 Interrupt Enable Acc
Page 65 and 66: MC95FG0128priority than high interr
Page 67 and 68: MC95FG0128INT10EINT9EINT8EINT7EINT6
Page 69 and 70: MC95FG01280 Disable1 EnableINT34E R
Page 71 and 72: MC95FG012811. Peripheral Hardware11
Page 73 and 74: MC95FG0128CS[1:0]Note2) if XINENA b
Page 75 and 76: MC95FG012811.2 BIT11.2.1 OverviewTh
Page 77 and 78: MC95FG012811.3 WDT11.3.1 OverviewTh
Page 79 and 80: MC95FG012811.3.6 WDT Interrupt Timi
Page 81 and 82: MC95FG012811.4.4 Watch Timer Regist
Page 83 and 84: MC95FG012811.5 Timer/PWM11.5.1 8-bi
Page 85 and 86: MC95FG0128Match with T0DR/T1DRT0DR/
Page 87 and 88: MC95FG0128T0CRT0EN T0PE CAP0 T0CK2
Page 89 and 90: MC95FG012811.5.1.5 16 Bit Capture M
Page 91 and 92: MC95FG0128Source Clock(f X)T1 00 01
Page 93 and 94:
MC95FG0128T0EN Control Timer 00 Tim
Page 95 and 96:
MC95FG0128T1 (Timer 1 Register: Rea
Page 97 and 98:
MC95FG012811.5.2.3 16-Bit Capture M
Page 99 and 100:
MC95FG0128Source Clock(f X)Tx 00 01
Page 101 and 102:
MC95FG01282F38H7 6 5 4 3 2 1 0TxEN
Page 103 and 104:
MC95FG0128PWM2HDR, PWM3HDR, PWM4HDR
Page 105 and 106:
MC95FG012811.6 Buzzer Driver11.6.1
Page 107 and 108:
MC95FG012811.7 USART11.7.1 Overview
Page 109 and 110:
MC95FG012811.7.3 Clock GenerationUB
Page 111 and 112:
MC95FG012811.7.6 Data formatA seria
Page 113 and 114:
MC95FG012811.7.8.3 Parity Generator
Page 115 and 116:
MC95FG0128RxDIDLESTARTBIT0Sample(U2
Page 117 and 118:
MC95FG0128XCK(UCPOL=0)XCK(UCPOL=1)S
Page 119 and 120:
MC95FG0128UCTRL11 FAH R/W 00H USART
Page 121 and 122:
MC95FG0128TXERXEUSARTENU2X0 Interru
Page 123 and 124:
MC95FG0128Jan 16, 2012 Ver.2.6 123
Page 125 and 126:
MC95FG012811.7.14 Baud Rate setting
Page 127 and 128:
MC95FG012811.8.3 Data Transmit / Re
Page 129 and 130:
MC95FG012811.8.7 SPI Register descr
Page 131 and 132:
MC95FG012811.9 I 2 C11.9.1 Overview
Page 133 and 134:
MC95FG0128PSDAMSBAcknowledgementSig
Page 135 and 136:
MC95FG0128Note that when a I 2 C in
Page 137 and 138:
MC95FG0128The next figure depicts a
Page 139 and 140:
MC95FG0128STOP bit in I2CMR.4) No A
Page 141 and 142:
MC95FG0128The next figure shows flo
Page 143 and 144:
MC95FG0128IDLES or SrSLA+WGCALL0x95
Page 145 and 146:
MC95FG0128I2CSR (I 2 C Status Regis
Page 147 and 148:
MC95FG0128GCALLENThis bit decides w
Page 149 and 150:
MC95FG0128AnalogInputAN0 ~ AN14Anal
Page 151 and 152:
MC95FG012811.10.6 Register descript
Page 153 and 154:
MC95FG012811.11 CALCULATOR_AI11.11.
Page 155 and 156:
MC95FG012811.11.3 Calculator Librar
Page 157 and 158:
MC95FG012812. Power Down Operation1
Page 159 and 160:
MC95FG0128The source for exit from
Page 161 and 162:
MC95FG012812.5.1 Register MapTable
Page 163 and 164:
MC95FG012813.4 RESET Noise Cancelle
Page 165 and 166:
MC95FG0128:VDD Input:Internal OSCRe
Page 167 and 168:
MC95FG012813.7 Brown Out Detector P
Page 169 and 170:
MC95FG0128PORFEXTRFWDTRFOCDRFBODRFB
Page 171 and 172:
MC95FG0128FormatconverterTarget MCU
Page 173 and 174:
MC95FG012814.2.2.2 Bit transferDSDA
Page 175 and 176:
MC95FG012815. Memory Programming15.
Page 177 and 178:
MC95FG0128WRITEREADnFERSTnPBRST0 0
Page 179 and 180:
MC95FG0128Program and erase time is
Page 181 and 182:
MC95FG012811 10 9 8 7 6 5 4 3 2 1 0
Page 183 and 184:
MC95FG0128Master ResetPage Buffer R
Page 185 and 186:
MC95FG0128(Only main cell area is e
Page 187 and 188:
MC95FG0128(1) Write 0xA5 to FEDR.(2
Page 189 and 190:
MC95FG0128Jan 16, 2012 Ver.2.6 189
Page 191 and 192:
MC95FG0128nRD H H H H H H H H H H H
Page 193 and 194:
MC95FG012815.6 Mode entrance method
Page 195 and 196:
MC95FG012816. Configure option16.1
Page 197 and 198:
MC95FG0128XRL A,dir Exclusive-OR di
Page 199 and 200:
MC95FG0128B. Package relationMC95FG
show all

MC95FG0128 - abov.co.kr

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?