MC95FG0128 - abov.co.kr

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MC95FG01287.12 SPI CharacteristicsTable 7-12 SPI Characteristics(VDD=5.0V±10%, VSS=0V, TA=-40~+85℃)Parameter Symbol PIN MIN TYP MAX UnitOutput Clock Pulse Period tSCK SCK -SPIclockmodeInput Clock Pulse Period tSCK SCK 2 tSYS - - nsInput Clock “H” or “L” Pulse Width tSCKL, tSCKH SCK50%duty-ns- nsInput Clock Pulse Transition Time tFSCK,tRSCK SCK - - 30 nsOutput Clock “H” or “L” PulseWidthOutput Clock Pulse TransitionTimeFirst Output Clock Delays Time tFOD OUTPUTtSCKL, tSCKH SCK tSYS-30 - - nstFSCK,tRSCK SCK - - 30 nsOutput Clock Delay Time tDS OUTPUT - - 100 nsInput Pulse Transition Time tFSIN,tRSIN INPUT - - 30 nsInput Setup Time tDIS INPUT 100 - nsInput Hold Time tDIH INPUT tSYS+70 - - ns/SS(Output/Input)tFODtSCKSCK(CPOL=0)(Output/Input)tSCKLtSCKH0.8VDD0.2VDDSCK(CPOL=1)(Output/Input)tDIStDIHtFSCKtRSCKMISO/MOSI(Data Input)MSBLSBtDStRSINtFSINMOSI/MISO(Data Output)MSBLSBFigure 7-2 SPI Timing40 Jan 16, 2012 Ver.2.6
MC95FG01287.13 Typical CharacteristicsThese graphs and tables provided in this section are for design guidance only and are not tested orguaranteed. In some graphs or tables the data presented are outside specified operating range (e.g.outside specified VDD range). This is for information only and devices are guaranteed to operateproperly only within the specified range.The data presented in this section is a statistical summary of data collected on units from differentlots over a period of time. “Typical” represents the mean of the distribution while “max” or “min”represents (mean + 3σ) and (mean - 3σ) respectively where σ is standard deviation.Jan 16, 2012 Ver.2.6 41
Page 1 and 2: MC95FG0128ABOV SEMICONDUCTOR Co., L
Page 3 and 4: MC95FG0128Published by FAE Team2009
Page 5 and 6: MC95FG012810.5 Interrupt Sequence .
Page 8 and 9: MC95FG0128Figure 11-15 PWM Mode ...
Page 10 and 11: MC95FG0128MC95FG01281. OverviewCMOS
Page 12 and 13: MC95FG01281.4 Development Tools1.4.
Page 14 and 15: MC95FG01282. Block DiagramnTESTDSCL
Page 19 and 20: DSDAP20/AN0/AVREFP21/AN1DSCLP22/AN2
Page 24 and 25: MC95FG0128Figure 4-3 80 pin MQFP pa
Page 26 and 27: MC95FG0128Figure 4-5 64 pin LQFP14
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Page 44 and 45: MC95FG01288.2 Data MemoryFigure 8-2
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Page 48 and 49: MC95FG01288.4.2 Compiler Compatible
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Page 59 and 60: MC95FG012810.4 Interrupt Vector Tab
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Page 79 and 80: MC95FG012811.3.6 WDT Interrupt Timi
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Page 83 and 84: MC95FG012811.5 Timer/PWM11.5.1 8-bi
Page 85 and 86: MC95FG0128Match with T0DR/T1DRT0DR/
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MC95FG0128Source Clock(f X)T1 00 01
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MC95FG0128T0EN Control Timer 00 Tim
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MC95FG0128T1 (Timer 1 Register: Rea
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MC95FG012811.5.2.3 16-Bit Capture M
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MC95FG0128Source Clock(f X)Tx 00 01
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MC95FG01282F38H7 6 5 4 3 2 1 0TxEN
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MC95FG0128PWM2HDR, PWM3HDR, PWM4HDR
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MC95FG012811.6 Buzzer Driver11.6.1
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MC95FG012811.7 USART11.7.1 Overview
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MC95FG012811.7.3 Clock GenerationUB
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MC95FG012811.7.6 Data formatA seria
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MC95FG012811.7.8.3 Parity Generator
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MC95FG0128RxDIDLESTARTBIT0Sample(U2
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MC95FG0128XCK(UCPOL=0)XCK(UCPOL=1)S
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MC95FG0128UCTRL11 FAH R/W 00H USART
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MC95FG0128TXERXEUSARTENU2X0 Interru
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MC95FG0128Jan 16, 2012 Ver.2.6 123
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MC95FG012811.7.14 Baud Rate setting
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MC95FG012811.8.3 Data Transmit / Re
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MC95FG012811.8.7 SPI Register descr
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MC95FG012811.9 I 2 C11.9.1 Overview
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MC95FG0128PSDAMSBAcknowledgementSig
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MC95FG0128Note that when a I 2 C in
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MC95FG0128The next figure depicts a
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MC95FG0128STOP bit in I2CMR.4) No A
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MC95FG0128The next figure shows flo
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MC95FG0128IDLES or SrSLA+WGCALL0x95
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MC95FG0128I2CSR (I 2 C Status Regis
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MC95FG0128GCALLENThis bit decides w
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MC95FG0128AnalogInputAN0 ~ AN14Anal
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MC95FG012811.10.6 Register descript
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MC95FG012811.11 CALCULATOR_AI11.11.
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MC95FG012811.11.3 Calculator Librar
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MC95FG012812. Power Down Operation1
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MC95FG0128The source for exit from
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MC95FG012812.5.1 Register MapTable
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MC95FG012813.4 RESET Noise Cancelle
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MC95FG0128:VDD Input:Internal OSCRe
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MC95FG012813.7 Brown Out Detector P
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MC95FG0128PORFEXTRFWDTRFOCDRFBODRFB
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MC95FG0128FormatconverterTarget MCU
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MC95FG012814.2.2.2 Bit transferDSDA
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MC95FG012815. Memory Programming15.
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MC95FG0128WRITEREADnFERSTnPBRST0 0
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MC95FG0128Program and erase time is
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MC95FG012811 10 9 8 7 6 5 4 3 2 1 0
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MC95FG0128Master ResetPage Buffer R
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MC95FG0128(Only main cell area is e
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MC95FG0128(1) Write 0xA5 to FEDR.(2
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MC95FG0128Jan 16, 2012 Ver.2.6 189
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MC95FG0128nRD H H H H H H H H H H H
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MC95FG012815.6 Mode entrance method
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MC95FG012816. Configure option16.1
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MC95FG0128XRL A,dir Exclusive-OR di
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MC95FG0128B. Package relationMC95FG
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