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<strong>MC95FG0128</strong>9. I/O Ports9.1 I/O PortsThe <strong>MC95FG0128</strong> has eleven I/O ports (P0 ~ PA). Each port can be easily <strong>co</strong>nfigured by softwareas I/O pin, internal pull up and open drain pin to meet various system <strong>co</strong>nfigurations and designrequirements. Also P0, P7 include function that can generate interrupt ac<strong>co</strong>rding to change of state ofthe pin.9.2 Port Register9.2.1 Data Register (Px)Data Register is a bidirectional I/O port. If ports are <strong>co</strong>nfigured as output ports, data can be written tothe <strong>co</strong>rresponding bit of the Px. If ports are <strong>co</strong>nfigured as input ports, the data can be read from the<strong>co</strong>rresponding bit of the Px.9.2.2 Direction Register (PxIO)Each I/O pin can independently used as an input or an output through the PxIO register. Bits clearedin this read/write register will select the <strong>co</strong>rresponding pin in Px to be<strong>co</strong>me an input, setting a bit setsthe pin to output. All bits are cleared by a system reset.9.2.3 Pull-up Resistor Selection Register (PxPU)The on-chip pull-up resistor can be <strong>co</strong>nnected to them in 1-bit units with a pull-up resistor selectionregister (PxPU). The pull-up register selection <strong>co</strong>ntrols the pull-up resister enable/disable of each port.When the <strong>co</strong>rresponding bit is 1, the pull-up resister of the pin is enabled. When 0, the pull-up resisteris disabled. All bits are cleared by a system reset.9.2.4 Open-drain Selection Register (PxOD)There is internally open-drain selection register (PxOD) in P0 ~ PA. The open-drain selection register<strong>co</strong>ntrols the open-drain enable/disable of each port. Ports be<strong>co</strong>me push-pull by a system reset. Youshould <strong>co</strong>nnect an internal resistor or an external resistor in open-drain output mode.9.2.5 Debounce Enable Register (PxDB)P0 ~ PA support debounce function. Debounce time of each ports has 5us9.2.6 Pin Change Interrupt Enable Register (PCIx)The P0, P7 can support Pin Change Interrupt function. Pin Change Interrupts PCI will trigger if anyenabled P0[7:0], P7[7:0] pin toggles. The PCIx Register <strong>co</strong>ntrol which pins <strong>co</strong>ntribute to the pinchange interrupts.Jan 16, 2012 Ver.2.6 51
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