HT46R23 8-Bit A/D Type OTP MCU

HT46R238-Bit A/D Type OTP MCUFeaturesOperating voltage:f SYS =4MHz: 3.3V~5.5Vf SYS =8MHz: 4.5V~5.5V23 bidirectional I/O lines (max.)1 interrupt input shared with an I/O line16-bit programmable timer/event counter with overflowinterrupt and 7-stage prescalerOn-chip crystal and RC oscillatorWatchdog Timer409615 program memory PROM1928 data memory RAMSupports PFD for sound generationHALT function and wake-up feature reduce powerconsumptionUp to 0.5s instruction cycle with 8MHz system clockat V DD =5V8-level subroutine nesting8 channels 10-bit resolution (9-bit accuracy) A/D converter2-channel (6+2)/(7+1)-bit PWM output shared withtwo I/O linesBit manipulation instruction15-bit table read instruction63 powerful instructionsAll instructions in one or two machine cyclesLow voltage reset functionI 2 C BUS (slave mode)24/28-pin SKDIP/SOP packageGeneral DescriptionThe device is an 8-bit high performance RISC-likemicrocontroller designed for multiple I/O product applications.It is particularly suitable for use in productssuch as washing machine controllers and home appliances.A HALT feature is included to reduce power consumption.The program and option memories can be electricallyprogrammed, making this microcontroller suitable forproduct development applications.I 2 C is a trademark of Philips Semiconductors.Rev. 1.40 1 February 8, 2002

HT46R23Block Diagram2 ) # 1 62 H C H= 4 2 H C H= + K JA H5 6 ) + 1 JA HHK F J+ EH? K EJ1 6 +6 46 4 +2 ) ! 2 ,7:2 HA I ? = A H B5 ; 52 ) " 6 42 ) "5 ; 5 + "1 I JHK ? JE 4 A C EI JA H 2 7:1 I JHK ? JE , A ? @ A H6 E E C/ A A H= J H 5 + 5 + 4 - 58 , ,8 5 5) 75 D EBJA H) + + 7 : 8 4, ) 6 ) A HO5 6 ) 6 7 52 ) ! 2 ) # F JE 2 4 9 , 62 HA I ? = A H2 9 2 , +2 ,2 * +2 *2 ) +2 )2 4 6 ,& + D = A ) , + L A HJA H1+ * 7 55 = L A @ A2 +2 + +2 4 6 *2 4 6 )9 , 67:4 + 5 +2 , 2 9 2 , 2 9 2 * ) 2 * % ) %2 ) 2 )2 ) ! 2 ,2 ) " 6 42 ) # 1 62 ) $ 5 , )2 ) % 5 + 2 + 2 + "Pin Assignment2 * # ) #2 * " ) "2 ) ! 2 ,2 )2 ) 2 ) 2 * ! ) !2 * ) 2 * ) 2 * ) 8 5 52 + !"#$%&' "! ' & % $ # " !0 6 " $ 4 ! " 5 , 12 ) 5 2 )2 * $ ) $2 * % ) %2 ) " 6 42 ) # 1 62 ) $ 5 , )2 ) % 5 + 5 + 5 + 8 , ,4 - 52 , 2 9 2 + 2 * # ) #2 * " ) "2 ) ! 2 ,2 )2 ) 2 ) 2 * ! ) !2 * ) 2 * ) 2 * ) 8 5 52 + 2 + 2 +!"#$%&' ! "0 6 " $ 4 ! & 5 , 12 ) 5 2 )&%$#"! ' & % $ #2 * $ ) $2 * % ) %2 ) " 6 42 ) # 1 62 ) $ 5 , )2 ) % 5 + 5 + 5 + 8 , ,4 - 52 , 2 9 2 , 2 9 2 + "2 + !Rev. 1.40 2 February 8, 2002

HT46R23Pin DescriptionPin NamePB0/AN0PB1/AN1PB2/AN2PB3/AN3PB4/AN4PB5/AN5PB6/AN6PB7/AN7PA0~PA2PA3/PFDPA4/TMRPA5/INTPA6/SDAPA7/SCLI/OI/OI/OROM CodeOptionPull-highPull-highWake-upPA3 or PFDI/O or Serial BusVSS Negative power supply, ground.PC0~PC4 I/O Pull-highPD0/PWM0PD1/PWM1I/OPull-highI/O or PWMDescriptionBidirectional 8-bit input/output port. Software instructions determine theCMOS output, Schmitt trigger input with or without pull-high resistor (determinedby pull-high option: port option) or A/D input.Once a PB line is selected as an A/D input (by using software control), theI/O function and pull-high resistor are disabled automatically.Bidirectional 8-bit input/output port. Each bit can be configured as wake-upinput by ROM code option. Software instructions determine the CMOS outputor Schmitt trigger input with or without pull-high resistor (determined bypull-high options: bit option). The PFD, TMR and INT are pin-shared withPA3, PA4 and PA5, respectively. Once the I 2 C BUS function is used, the internalregisters related to PA6 and PA7 can not be used.Bidirectional 5-bit input/output port. Software instructions determine theCMOS output, Schmitt trigger input with or without pull-high resistor (determineby pull-high option: port option).Bidirectional 2-bit input/output port. Software instructions determine theCMOS output, Schmitt trigger input with or without a pull-high resistor (determinedby pull-high option: port option). The PWM0/PWM1 output functionare pin-shared with PD0/PD1 (dependent on PWM optios).RES I Schmitt trigger reset input. Active low.VDD Positive power supplyOSC1OSC2IOCrystalor RCOSC1, OSC2 are connected to an RC network or a Crystal (determined byROM code option) for the internal system clock. In the case of RC operation,OSC2 is the output terminal for 1/4 system clock.Absolute Maximum RatingsSupply Voltage ...........................V SS 0.3V to V SS +5.5VInput Voltage..............................V SS 0.3V to V DD +0.3VStorage Temperature ............................50C to125COperating Temperature...........................40C to85CNote: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings maycause substantial damage to the device. Functional operation of this device at other conditions beyond thoselisted in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.Rev. 1.40 3 February 8, 2002

HT46R23D.C. CharacteristicsTa=25CSymbolParameterV DDTest ConditionsConditionsMin. Typ. Max. UnitV DD1 Operating Voltage f SYS =4MHz 3.3 5.5 VV DD2 Operating Voltage f SYS =8MHz 4.5 5.5 VI DD1Operating Current (Crystal OSC)3.3V No load, fSYS =4MHz 1.3 3 mA5V ADC disable 3.3 5 mAI DD2Operating Current (RC OSC)I DD3 Operating Current 5VI ADCOnly ADC Enable, Others Disable3.3V No load, fSYS =4MHz 1.3 3 mA5V ADC disable 3.3 5 mANo load, fsys=8MHzADC disable 4 8 mA3.3V 1 2 mANo load5V 2 4 mAI STB1I STB2Standby Current (WDT Enabled)Standby Current (WDT Disabled)3.3V 5 ANo load, system HALT5V 10 A3.3V 1 ANo load, system HALT5V 2 AV AD A/D Input Voltage 0 V DD VV IL1V IH1V IL2V IH2Input Low Voltage for I/O Ports,TMR and INTInput High Voltage for I/O Ports,TMR and INTInput Low Voltage (RES)Input High Voltage (RES)3.3V 0 0.3V DD V5V 0 0.3V DD V3.3V 0.7V DD V DD V5V 0.7V DD V DD V3.3V 0 0.4V DD V5V 0 0.4V DD V3.3V 0.9V DD V DD V5V 0.9V DD V DD VV LVR Low Voltage Reset 2.7 3 3.3 VI OLI OHR PHI/O Port Sink CurrentI/O Port Source CurrentPull-high Resistance3.3V V OL =0.1V DD 4 8 mA5V V OL =0.1V DD 10 20 mA3.3V V OH =0.9V DD 2 4 mA5V V OH =0.9V DD 5 10 mA3.3V 40 60 80 k5V 10 30 50 kE AD A/D Conversion Error 0.5 1 LSBRev. 1.40 4 February 8, 2002

HT46R23A.C. CharacteristicsTa=25CSymbolParameterV DDTest ConditionsConditionsMin. Typ. Max. Unitf SYS1f SYS2f TIMERSystem Clock (Crystal OSC)System Clock (RC OSC)Timer I/P Frequency (TMR)3.3V 400 4000 kHz5V 400 8000 kHz3.3V 400 4000 kHz5V 400 8000 kHz3.3V 0 4000 kHz5V 0 8000 kHzt AD A/D Clock Period 5V 1 st ADC A/D Conversion Time 76 t ADt WDTOSCWatchdog Oscillator3.3V 43 86 168 s5V 36 72 144 st RES External Reset Low Pulse Width 1 st SST System Start-up Timer Period Power-up, reset orwake-up from HALT 1024 *t SYSt INT Interrupt Pulse Width 1 st HBUS I 2 C BUS Clock Period Note: *t SYS =1/f SYSConnect to externalpull-high resistor 2k64 *t SYSRev. 1.40 5 February 8, 2002

HT46R23Functional DescriptionExecution flowThe system clock for the microcontroller is derived fromeither a crystal or an RC oscillator. The system clock isinternally divided into four non-overlapping clocks. Oneinstruction cycle consists of four system clock cycles.Instruction fetching and execution are pipelined in sucha way that a fetch takes an instruction cycle while decodingand execution takes the next instruction cycle.However, the pipelining scheme causes each instructionto effectively execute in a cycle. If an instructionchanges the program counter, two cycles are required tocomplete the instruction.Program counter PCThe program counter (PC) controls the sequence inwhich the instructions stored in program PROM are executedand its contents specify full range of programmemory.After accessing a program memory word to fetch an instructioncode, the contents of the program counter areincremented by one. The program counter then points tothe memory word containing the next instruction code.When executing a jump instruction, conditional skip execution,loading PCL register, subroutine call, initial reset,internal interrupt, external interrupt or return fromsubroutine, the PC manipulates the program transfer byloading the address corresponding to each instruction.The conditional skip is activated by instructions. Oncethe condition is met, the next instruction, fetched duringthe current instruction execution, is discarded and adummy cycle replaces it to get the proper instruction.Otherwise proceed with the next instruction.The lower byte of the program counter (PCL) is a readableand writeable register (06H). Moving data into thePCL performs a short jump. The destination will bewithin 256 locations.When a control transfer takes place, an additionaldummy cycle is required.5 O I JA + ? 6 6 6 ! 6 " 6 6 6 ! 6 " 6 6 6 ! 6 " 5 + 4 + O 2 +2 + 2 + 2 + A J? D 1 5 6 2 + - N A ? K JA 1 5 6 2 + A J? D 1 5 6 2 + - N A ? K JA 1 5 6 2 + A J? D 1 5 6 2 + - N A ? K JA 1 5 6 2 + Execution flowModeProgram Counter*11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0Initial Reset 0 0 0 0 0 0 0 0 0 0 0 0External Interrupt 0 0 0 0 0 0 0 0 0 1 0 0Timer/Event Counter Overflow 0 0 0 0 0 0 0 0 1 0 0 0A/D Converter Interrupt 0 0 0 0 0 0 0 0 1 1 0 0I 2 C BUS Interrupt 0 0 0 0 0 0 0 1 0 0 0 0SkipPC+2Loading PCL *11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0Jump, Call Branch #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0Return from Subroutine S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0Program counterNote: *11~*0: Program counter bitsS11~S0: Stack register bits#11~#0: Instruction code bits @7~@0: PCL bitsRev. 1.40 6 February 8, 2002

HT46R23Program memory PROMThe program memory is used to store the program instructionswhich are to be executed. It also containsdata, table, and interrupt entries, and is organized into409615 bits, addressed by the program counter and tablepointer.Certain locations in the program memory are reservedfor special usage: Location 000HThis area is reserved for program initialization. Afterchip reset, the program always begins execution at location000H. Location 004HThis area is reserved for the external interrupt serviceprogram. If the INT input pin is activated, the interruptis enabled and the stack is not full, the program beginsexecution at location 004H. Location 008HThis area is reserved for the timer/event counter interruptservice program. If a timer interrupt results from atimer/event counter overflow, and if the interrupt is enabledand the stack is not full, the program begins executionat location 008H. 0 " 0 & 0 + 0 0 0 0 0 0, A L E? A 1 EJE= E = JE 2 H C H= - N JA H = 1 JA HHK F J5 K > H K JE A6 E A H- L A J+ K JA H1 JA HHK F J5 K > H K JE A ) , + L A HJA H1 JA HHK F J5 K > H K JE A0 * 7 5 1 JA HHK F J5 K > H K JE A K F 6 = > A # $ M H@ I K F 6 = > A # $ M H@ I # > EJI JA H= C A I BH J 2 H C H= A HO Location 00CHThis area is reserved for the A/D converter interruptservice program. If an A/D converter interrupt resultsfrom an end of A/D conversion, and if the interrupt isenabled and the stack is not full, the program beginsexecution at location 00CH. Location 010HThis area is reserved for the I 2 C BUS interrupt serviceprogram. If the I 2 C BUS interrupt resulting from aslave address is match or completed one byte of datatransfer, and if the interrupt is enable and the stack isnot full, the program begins execution at location010H. Table locationAny location in the PROM space can be used aslook-up tables. The instructions TABRDC [m] (thecurrent page, 1 page=256 words) and TABRDL [m](the last page) transfer the contents of the lower-orderbyte to the specified data memory, and thehigher-order byte to TBLH (08H). Only the destinationof the lower-order byte in the table is well-defined, theother bits of the table word are transferred to the lowerportion of TBLH, and the remaining 1 bit is read as 0.The Table Higher-order byte register (TBLH) is readonly. The table pointer (TBLP) is a read/write register(07H), which indicates the table location. Before accessingthe table, the location must be placed inTBLP. The TBLH is read only and cannot be restored.If the main routine and the ISR (Interrupt Service Routine)both employ the table read instruction, the contentsof the TBLH in the main routine are likely to bechanged by the table read instruction used in the ISR.Errors can occur. In other words, using the table readinstruction in the main routine and the ISR simultaneouslyshould be avoided. However, if the table readinstruction has to be applied in both the main routineand the ISR, the interrupt is supposed to be disabledprior to the table read instruction. It will not be enableduntil the TBLH has been backed up. All table relatedinstructions require two cycles to complete the operation.These areas may function as normal programmemory depending upon the requirements.Program memoryInstructionTable Location*11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0TABRDC [m] P11 P10 P9 P8 @7 @6 @5 @4 @3 @2 @1 @0TABRDL [m] 1 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0Table locationNote: *11~*0: Table location bitsP11~P8: Current program counter bits@7~@0: Table pointer bitsRev. 1.40 7 February 8, 2002

HT46R23Stack register STACKThis is a special part of the memory which is used tosave the contents of the program counter (PC) only. Thestack is organized into 8 levels and is neither part of thedata nor part of the program space, and is neither readablenor writeable. The activated level is indexed by thestack pointer (SP) and is neither readable nor writeable.At a subroutine call or interrupt acknowledgment, thecontents of the program counter are pushed onto thestack. At the end of a subroutine or an interrupt routine,signaled by a return instruction (RET or RETI), the programcounter is restored to its previous value from thestack. After a chip reset, the SP will point to the top of thestack.If the stack is full and a non-masked interrupt takesplace, the interrupt request flag will be recorded but theacknowledgment will be inhibited. When the stackpointer is decremented (by RET or RETI), the interruptwill be serviced. This feature prevents stack overflow allowingthe programmer to use the structure more easily.In a similar case, if the stack is full and a CALL is subsequentlyexecuted, stack overflow occurs and the firstentry will be lost (only the most recent 8 return addressesare stored).Data memory RAMThe data memory is designed with 2248 bits. Thedata memory is divided into two functional groups: specialfunction registers and general purpose data memory(1928). Most are read/write, but some are readonly.The special function registers include the indirect addressingregisters (00H;02H), timer/event counterhigher-order byte register (TMRH;0CH), timer/eventcounter low-order byte register (TMRL;0DH),timer/event counter control register (TMRC;0EH), programcounter lower-order byte register (PCL;06H),memory pointer registers (MP0;01H, MP1;03H), accumulator(ACC;05H), table pointer (TBLP;07H), tablehigher-order byte register (TBLH;08H), status register(STATUS;0AH), interrupt control register (INTC0; 0BH),PWM data register (PWM0;1AH, PWM1;1BH), the I 2 CBUS slave address register (HADR;20H), the I 2 C BUScontrol register (HCR;21H), the I 2 C BUS status register(HSR;22H), the I 2 C BUS data register (HDR;23H), theA/D result lower-order byte register (ADRL;24H), theA/D result higher-order byte register (ADRH;25H), theA/D control register (ADCR;26H), the A/D clock settingregister (ACSR;27H), I/O registers (PA;12H, PB;14H,PC;16H, PD;18H) and I/O control registers (PAC;13H,PBC;15H, PCC;17H, PDC;19H). The remaining spacebefore the 40H is reserved for future expanded usageand reading these locations will get 00H. The generalpurpose data memory, addressed from 40H to FFH, isused for data and control information under instructioncommands. 0 0 0 ! 0 " 0 # 0 $ 0 % 0 & 0 ' 0 ) 0 * 0 + 0 , 0 - 0 0 0 0 0 ! 0 " 0 # 0 $ 0 % 0 & 0 ' 0 ) 0 * 0 + 0 , 0 - 0 0 0 00! 0" 0# 0$ 0% 0& 0! 0" 0 01 @ EHA ? J) @ @ HA I I E C 4 A C EI JA H 2 1 @ EHA ? J) @ @ HA I I E C 4 A C EI JA H 2 ) + +2 + 6 * 26 * 05 6 ) 6 7 51 6 + 6 4 06 4 6 4 +2 )2 ) +2 *2 * +2 +2 + +2 ,2 , +2 9 2 9 1 6 + 0 ) , 40 + 40 5 40 , 4) , 4 ) , 4 0) , + 4) + 5 4/ A A H= 2 K HF I A, ) 6 ) - 4 ; ' * O JA I RAM mapping5 F A ? E= 2 K HF I A, ) 6 ) - 4 ;7 K I A @4 A = @ = I All of the data memory areas can handle arithmetic,logic, increment, decrement and rotate operations directly.Except for some dedicated bits, each bit in thedata memory can be set and reset by SET [m].i andCLR [m].i. They are also indirectly accessible throughmemory pointer registers (MP0;01H/MP1;03H).Rev. 1.40 8 February 8, 2002

HT46R23Indirect addressing registerLocation 00H and 02H are indirect addressing registersthat are not physically implemented. Any read/write operationof [00H] or [02H] will access data memorypointed to by MP0[01H] or MP1[03H] respectively.Reading location 00H or 02H itself indirectly will returnthe result 00H. Writing indirectly result in no operation.The memory pointer registers (MP0 and MP1 are 8-bitregisters).AccumulatorThe accumulator is closely related to ALU operations. Itis also mapped to location 05H of the data memory andcan carry out immediate data operations. The datamovement between two data memory locations mustpass through the accumulator.operations related to the status register may give differentresults from those intended. The TO flag canbe affected only by system power-up, a WDTtime-out or executing the CLR WDT or HALT instruction.The PD flag can be affected only by executingthe HALT or CLR WDT instruction or asystem power-up.The Z, OV, AC and C flags generally reflect the status ofthe latest operations.In addition, on entering the interrupt sequence or executingthe subroutine call, the status register will not bepushed onto the stack automatically. If the contents ofthe status are important and if the subroutine can corruptthe status register, precautions must be taken tosave it properly.Arithmetic and logic unit ALUThis circuit performs 8-bit arithmetic and logic operations.The ALU provides the following functions: Arithmetic operations (ADD, ADC, SUB, SBC, DAA) Logic operations (AND, OR, XOR, CPL) Rotation (RL, RR, RLC, RRC) Increment and Decrement (INC, DEC) Branch decision (SZ, SNZ, SIZ, SDZ ....)The ALU not only saves the results of a data operation butalso changes the status register.Status register STATUSThis 8-bit register (0AH) contains the zero flag (Z), carryflag (C), auxiliary carry flag (AC), overflow flag (OV),power down flag (PD), and watchdog time-out flag (TO).It also records the status information and controls theoperation sequence.With the exception of the TO and PD flags, bits in thestatus register can be altered by instructions likemost other registers. Any data written into the statusregister will not change the TO or PD flag. In additionLabels Bits FunctionInterruptThe device provides an external interrupt, an internaltimer/event counter interrupt, the A/D converter interruptand the I 2 C BUS interrupts. The interrupt control register0 (INTC0;0BH) and interrupt control register 1(INTC1;1EH) contains the interrupt control bits to set theenable/disable and the interrupt request flags.Once an interrupt subroutine is serviced, all the other interruptswill be blocked (by clearing the EMI bit). Thisscheme may prevent any further interrupt nesting. Otherinterrupt requests may happen during this interval butonly the interrupt request flag is recorded. If a certain interruptrequires servicing within the service routine, theEMI bit and the corresponding bit of INTC0 and INTC1may be set to allow interrupt nesting. If the stack is full,the interrupt request will not be acknowledged, even if therelated interrupt is enabled, until the SP is decremented.If immediate service is desired, the stack must be preventedfrom becoming full.All these kinds of interrupts have a wake-up capability.As an interrupt is serviced, a control transfer occurs bypushing the program counter onto the stack, followed byC 0C is set if the operation results in a carry during an addition operation or if a borrow does nottake place during a subtraction operation; otherwise C is cleared. C is also affected by a rotatethrough carry instruction.AC 1AC is set if the operation results in a carry out of the low nibbles in addition or no borrow fromthe high nibble into the low nibble in subtraction; otherwise AC is cleared.Z 2 Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.OV 3OV is set if the operation results in a carry into the highest-order bit but not a carry out of thehighest-order bit, or vice versa; otherwise OV is cleared.PD 4PD is cleared by system power-up or executing the CLR WDT instruction. PD is set by executingthe HALT instruction.TO 5TO is cleared by system power-up or executing the CLR WDT or HALT instruction. TO isset by a WDT time-out. 6, 7 Unused bit, read as 0Status registerRev. 1.40 9 February 8, 2002

HT46R23a branch to a subroutine at specified location in the programmemory. Only the program counter is pushed ontothe stack. If the contents of the register or status register(STATUS) are altered by the interrupt service programwhich corrupts the desired control sequence, the contentsshould be saved in advance.External interrupts are triggered by a high to low transitionof INT and the related interrupt request flag (EIF; bit4 of INTC0) will be set. When the interrupt is enabled,the stack is not full and the external interrupt is active, asubroutine call to location 04H will occur. The interruptrequest flag (EIF) and EMI bits will be cleared to disableother interrupts.The internal timer/event counter interrupt is initialized bysetting the timer/event counter interrupt request flag(TF; bit 5 of INTC0), caused by a timer overflow. Whenthe interrupt is enabled, the stack is not full and the TFbit is set, a subroutine call to location 08H will occur. Therelated interrupt request flag (TF) will be reset and theEMI bit cleared to disable further interrupts.The A/D converter interrupt is initialized by setting theA/D converter request flag (ADF; bit 6 of INTC0),caused by an end of A/D conversion. When the interruptis enabled, the stack is not full and the ADF is set, a subroutinecall to location 0CH will occur. The related interruptrequest flag (ADF) will be reset and the EMI bitcleared to disable further interrupts.Register Bit No. LabelINTC0(0BH)0 EMI1 EEI2 ETI3 EADI4 EIF5 TF6 ADFFunctionControls the master (global)interrupt(1= enabled; 0= disabled)Controls the external interrupt(1= enabled; 0= disabled)Controls the timer/eventcounter interrupt(1= enabled; 0= disabled)Controls the A/D converterinterrupt(1= enabled; 0= disabled)External interrupt request flag(1= active; 0= inactive)Internal timer/event counterrequest flag(1= active; 0= inactive)A/D converter request flag(1= active; 0= inactive)7 Unused bit, read as 0INTC0 registerThe I 2 C BUS interrupt is initialized by setting the I 2 C BUSinterrupt request flag (HIF; bit 4 of INTC1), caused by aslave address match (HAAS=1) or one byte of datatransfer is completed. When the interrupt is enabled, thestack is not full and the HIF bit is set, a subroutine call tolocation 10H will occur. The related interrupt request flag(HIF) will be reset and the EMI bit cleared to disable furtherinterrupts.During the execution of an interrupt subroutine, other interruptacknowledgments are held until the RETI instructionis executed or the EMI bit and the relatedinterrupt control bit are set to 1 (of course, if the stack isnot full). To return from the interrupt subroutine, RET orRETI may be invoked. RETI will set the EMI bit to enablean interrupt service, but RET will not.Interrupts, occurring in the interval between the risingedges of two consecutive T2 pulses, will be serviced onthe latter of the two T2 pulses, if the corresponding interruptsare enabled. In the case of simultaneous requeststhe following table shows the priority that is applied.These can be masked by resetting the EMI bit.No. Interrupt Source Priority Vectora External Interrupt 1 04Hb Timer/event Counter Overflow 2 08Hc A/D Converter Interrupt 3 0CHd I 2 C BUS Interrupt 4 10HThe timer/event counter interrupt request flag (TF), externalinterrupt request flag (EIF), A/D converter requestflag (ADF), the I 2 C BUS interrupt request flag (HIF), enabletimer/event counter bit (ETI), enable external interruptbit (EEI), enable A/D converter interrupt bit (EADI),enable I 2 C BUS interrupt bit (EHI) and enable master interruptbit (EMI) constitute an interrupt control register 0(INTC0) and an interrupt control register 1 (INTC1)which are located at 0BH and 1EH in the data memory.EMI, EEI, ETI, EADI, EHI are used to control the enabling/disablingof interrupts. These bits prevent the requestedinterrupt from being serviced. Once theinterrupt request flags (TF, EIF, ADF, HIF) are set, theywill remain in the INTC0 and INTC1 register until the interruptsare serviced or cleared by a software instruction.Register Bit No. LabelINTC1(1EH)0 EHIFunctionControls the I 2 C BUS interrupt(1= enabled; 0= disabled)1 Unused bit, read as 02 Unused bit, read as 03 Unused bit, read as 04 HIF I2 C BUS interrupt requestflag (1= active; 0= inactive)5 Unused bit, read as 06 Unused bit, read as 07 Unused bit, read as 0INTC1 registerRev. 1.40 10 February 8, 2002

HT46R23It is recommended that a program does not use theCALL subroutine within the interrupt subroutine. Interruptsoften occur in an unpredictable manner orneed to be serviced immediately in some applications.If only one stack is left and enabling the interrupt is notwell controlled, the original control sequence will be damagedonce the CALL operates in the interrupt subroutine.Oscillator configurationThere are two oscillator circuits in the microcontroller. 5 + 5 + 5 + B5 ; 5 " 5 + 5 F A , H= E+ HO I J= I ? E= J H 4 + I ? E= J HSystem oscillatorBoth are designed for system clocks, namely the RC oscillatorand the Crystal oscillator, which are determinedby the ROM code option. No matter what oscillator typeis selected, the signal provides the system clock. TheHALT mode stops the system oscillator and ignores anexternal signal to conserve power.If an RC oscillator is used, an external resistor betweenOSC1 and VSS is required and the resistance mustrange from 30k to 750k. The system clock, dividedby 4, is available on OSC2, which can be used to synchronizeexternal logic. The RC oscillator provides themost cost effective solution. However, the frequency ofoscillation may vary with VDD, temperatures and thechip itself due to process variations. It is, therefore, notsuitable for timing sensitive operations where an accurateoscillator frequency is desired.If the Crystal oscillator is used, a crystal across OSC1and OSC2 is needed to provide the feedback and phaseshift required for the oscillator, and no other externalcomponents are required. Instead of a crystal, a resonatorcan also be connected between OSC1 and OSC2 toget a frequency reference, but two external capacitors inOSC1 and OSC2 are required (If the oscillating frequencyis less than 1MHz).The WDT oscillator is a free running on-chip RC oscillator,and no external components are required. Even if the systementers the power down mode, the system clock isstopped, but the WDT oscillator still works with a period ofapproximately 72s@5V. The WDT oscillator can be disabledby ROM code option to conserve power.Watchdog Timer WDTThe clock source of the WDT is implemented by an dedicatedRC oscillator (WDT oscillator) or instruction clock(system clock divided by 4) decided by ROM code options.This timer is designed to prevent a software malfunctionor sequence jumping to an unknown locationwith unpredictable results. The watchdog timer can bedisabled by a ROM code option. If the watchdog timer isdisabled, all the executions related to the WDT result inno operation.Once an internal WDT oscillator (RC oscillator with period72s normally) is selected, it is divided by 2 12 ~2 15(by ROM code option to get the WDT time-out period).The minimum period of WDT time-out period is about300ms~600ms. This time-out period may vary with temperature,VDD and process variations. By selection theWDT ROM code option, longer time-out periods can berealized. If the WDT time-out is selected 2 15 , the maximumtime-out period is divided by 2 15 ~2 16 about2.3s~4.7s.If the WDT oscillator is disabled, the WDT clock may stillcone from the instruction clock and operate in the samemanner except that in the halt state the WDT may stopcounting and lose its protecting purpose. In this situationthe logic can only be restarted by external logic. If thedevice operates in a noisy environment, using theon-chip RC oscillator (WDT OSC) is strongly recommended,since the HALT will stop the system clock.The WDT overflow under normal operation will initializechip reset and set the status bit TO. Whereas in thehalt mode, the overflow will initialize a warm reset onlythe PC and SP are reset to zero. To clear the contents ofWDT, three methods are adopted; external reset (a lowlevel to RES), software instructions, or a HALT instruction.The software instructions include CLR WDT andthe other set - CLR WDT1 and CLR WDT2. Of these two5 O I JA + ? " = I F JE I A A ? JBIBI &, EL E@ A H 9 , 6 2 HA I ? = A H9 , 6 5 + = I F JE + 49 , 6 + A = H6 + 46 6 E A K J4 A I A J # $BI BI " #BI BI ! "BI BI !BI BI Watchdog TimerRev. 1.40 11 February 8, 2002

HT46R23types of instruction, only one can be active dependingon the ROM code option CLR WDT times selectionoption. IftheCLR WDT is selected (i.e. CLRWDTtimes equal one), any execution of the CLR WDT instructionwill clear the WDT. In case CLR WDT1 andCLR WDT2 are chosen (i.e. CLRWDT times equaltwo), these two instructions must be executed to clearthe WDT; otherwise, the WDT may reset the chip becauseof time-out.If the WDT time-out period is selected f s /2 12 (ROM codeoption), the WDT time-out period ranges fromf s /2 12 ~f s /2 13 , since the CLR WDT or CLR WDT1 andCLR WDT2 instructions only clear the last two stagesof the WDT.Power down operation HALTThe HALT mode is initialized by the HALT instructionand results in the following... The system oscillator will be turned off but the WDToscillator keeps running (if the WDT oscillator is selected). The contents of the on chip RAM and registers remainunchanged. WDT will be cleared and recounted again (if the WDTclock is from the WDT oscillator). All of the I/O ports maintain their original status. The PD flag is set and the TO flag is cleared.The system can leave the HALT mode by means of anexternal reset, an interrupt, an external falling edge signalon port A or a WDT overflow. An external resetcauses a device initialization and the WDT overflow performsa warm reset. After the TO and PD flags are examined,the reason for chip reset can be determined.The PD flag is cleared by system power-up or executingthe CLR WDT instruction and is set when executingthe HALT instruction. The TO flag is set if the WDTtime-out occurs, and causes a wake-up that only resetsthe PC and SP; the others keep their original status.the actual interrupt subroutine execution will be delayedby one or more cycles. If the wake-up results in the nextinstruction execution, this will be executed immediatelyafter the dummy period is finished.To minimize power consumption, all the I/O pins shouldbe carefully managed before entering the HALT status.ResetThere are three ways in which a reset can occur: RES reset during normal operation RES reset during HALT WDT time-out reset during normal operationThe WDT time-out during HALT is different from otherchip reset conditions, since it can perform a warm re -set that resets only the PC and SP, leaving the other circuitsin their original state. Some registers remain unchangedduring other reset conditions. Most registersare reset to the initial condition when the reset conditionsare met. By examining the PD and TO flags, theprogram can distinguish between different chip resets.8 , ,4 - 55 5 6 6 E A K J+ D EF 4 A I A JReset timing chart8 , ,4 - 5J5 5 6The port A wake-up and interrupt methods can be consideredas a continuation of normal execution. Each bitin port A can be independently selected to wake up thedevice by the ROM code option. Awakening from an I/Oport stimulus, the program will resume execution of thenext instruction. If it is awakening from an interrupt, twosequences may happen. If the related interrupt is disabledor the interrupt is enabled but the stack is full, theprogram will resume execution at the next instruction. Ifthe interrupt is enabled and the stack is not full, the regularinterrupt response takes place. If an interrupt requestflag is set to 1 before entering the HALT mode, thewake-up function of the related interrupt will be disabled.Once a wake-up event occurs, it takes 1024 t SYS (systemclock period) to resume normal operation. In otherwords, a dummy period will be inserted after wake-up. Ifthe wake-up results from an interrupt acknowledgment,0 ) 64 - 5 5 + 9 , 65 5 6 > EJ4 EF F A+ K JA H5 O I JA 4 A I A JReset circuitReset configuration9 = H 4 A I A J+ @4 A I A JRev. 1.40 12 February 8, 2002

HT46R23TO PD RESET Conditions0 0 RES reset during power-upu u RES reset during normal operation0 1 RES wake-up HALT1 u WDT time-out during normal operation1 1 WDT wake-up HALTNote: u means unchangedTo guarantee that the system oscillator is started andstabilized, the SST (System Start-up Timer) provides anextra-delay of 1024 system clock pulses when the systemreset (power-up, WDT time-out or RES reset) or thesystem awakes from the HALT state.When a system reset occurs, the SST delay is addedduring the reset period. Any wake-up from HALT will enablethe SST delay. The functional unit chip reset statusare shown below.PCInterruptWDTTimer/event CounterInput/output PortsSP000HDisableClear. After master reset, WDTbegins countingOffInput modePoints to the top of the stackThe registers states are summarized in the following table.RegisterRese t(Power On)WDT Time-out(Normal Operation)RES Reset(Normal Operation)RES Reset(HALT)WDT Time-out(HALT)*TMRL xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuuTMRH xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuuTMRC 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuuProgramCounter000H 000H 000H 000H 000HMP0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuuMP1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuuACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuuTBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuuTBLH -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuuSTATUS --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuuINTC0 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuuINTC1 ---0 ---0 ---0 ---0 ---0 ---0 ---0 ---0 ---u ---uPA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuuPAC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuuPB 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuuPBC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuuPC ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---u uuuuPCC ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---u uuuuPD ---- --11 ---- --11 ---- --11 ---- --11 ---- --uuPDC ---- --11 ---- --11 ---- --11 ---- --11 ---- --uuPWM0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuuPWM1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuuHADR xxxx xxx- xxxx xxx- xxxx xxx- xxxx xxx- uuuu uuu-HCR 0--0 0--- 0--0 0--- 0--0 0--- 0--0 0--- u--u u---HSR 100- -0-1 100- -0-1 100- -0-1 100- -0-1 uuu- -u-uHDR xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuuADRL xx-- ---- xx-- ---- xx-- ---- xx-- ---- uu-- ----ADRH xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuuRev. 1.40 13 February 8, 2002

HT46R23RegisterRese t(Power On)WDT Time-out(Normal Operation)RES Reset(Normal Operation)RES Reset(HALT)WDT Time-out(HALT)*ADCR 0100 0000 0100 0000 0100 0000 0100 0000 uuuu uuuuACSR 1--- --00 1--- --00 1--- --00 1--- --00 u--- --uuNote:* stands for warm resetu stands for unchangedx stands for unknownTimer/Event CounterA timer/event counter (TMR) is implemented in themicrocontroller. The timer/event counter contains an16-bit programmable count-up counter and the clockmay come from an external source or the system clock.Using the internal system clock, there is only one referencetime-base. The internal clock source comes fromf SYS . Using external clock input allows the user to countexternal events, measure time internals or pulse widths,or generate an accurate time base. While using the internalclock allows the user to generate an accurate timebase.There are three registers related to the timer/eventcounter; TMRH (0CH), TMRL (0DH), TMRC (0EH).Writing TMRL will only put the written data to an internallower-order byte buffer (8 bits) and writing TMRH willtransfer the specified data and the contents of thelower-order byte buffer to TMRH and TMRL preload registers,respectively. The timer/event counter preloadregister is changed by each writing TMRH operations.Reading TMRH will latch the contents of TMRH andTMRL counters to the destination and the lower-orderbyte buffer, respectively. Reading the TMRL will readthe contents of the lower-order byte buffer. The TMRC isthe timer/event counter control register, which definesthe operating mode, counting enable or disable and activeedge.The TM0, TM1 bits define the operating mode. Theevent count mode is used to count external events,which means the clock source comes from an external(TMR) pin. The timer mode functions as a normal timerwith the clock source coming from the f INT clock. Thepulse width measurement mode can be used to countthe high or low level duration of the external signal(TMR). The counting is based on the f INT .In the event count or timer mode, once the timer/eventcounter starts counting, it will count from the currentcontents in the timer/event counter to FFFFH. Onceoverflow occurs, the counter is reloaded from thetimer/event counter preload register and generates theinterrupt request flag (TF; bit 5 of INTC0) at the sametime.In the pulse width measurement mode with the TONand TE bits equal to one, once the TMR has received atransient from low to high (or high to low if the TE bits is0) it will start counting until the TMR returns to the originallevel and resets the TON. The measured result willremain in the timer/event counter even if the activatedtransient occurs again. In other words, only one cyclemeasurement can be done. Until setting the TON, thecycle measurement will function again as long as it receivesfurther transient pulse. Note that, in this operatingmode, the timer/event counter starts counting notaccording to the logic level but according to the transientedges. In the case of counter overflows, the counter isreloaded from the timer/event counter preload registerand issues the interrupt request just like the other twomodes. To enable the counting operation, the timer ONbit (TON; bit 4 of TMRC) should be set to 1. In the pulsewidth measurement mode, the TON will be cleared automaticallyafter the measurement cycle is completed.But in the other two modes the TON can only be reset by2 9 $ H% ? F = HA6 2 , 2 , ? EH? K EJB5 ; 5& I J= C A F HA I ? = A H& 7 :2 5 + 2 5 + 6 4B1 66 6 6 E A H- L A J+ K JA H2 HA = @ 4 A C EI JA H, = J= * K I4 A = @6 -6 6 6 2 K I A 9 E@ JD A = I K HA A J @ A + JH 6 E A H- L A J+ K JA H 2 , L A HB MJ 1 JA HHK F JTimer/Event CounterRev. 1.40 14 February 8, 2002

HT46R23instructions. The overflow of the timer/event counter isone of the wake-up sources. No matter what the operationmode is, writing a0toETIcandisable the interruptservice.In the case of timer/event counter OFF condition, writingdata to the timer/event counter preload register will alsoreload that data to the timer/event counter. But if thetimer/event counter is turned on, data written to it willonly be kept in the timer/event counter preload register.The timer/event counter will still operate until overflowoccurs. When the timer/event counter (reading TMRH)is read, the clock will be blocked to avoid errors. Asclock blocking may results in a counting error, this mustbe taken into consideration by the programmer.The bit0~bit2 of the TMRC can be used to define thepre-scaling stages of the internal clock sources oftimer/event counter. The definitions are as shown. Theoverflow signal of timer/event counter can be used togenerate the PFD signal. The timer prescaler is alsoused as the PWM counter.Label(TMRC) BitsPSC0~PSC20~2TE 3TON 4TM0TM1FunctionTo define the prescaler stages, PSC2,PSC1, PSC0=000: f INT =f SYS001: f INT =f SYS /2010: f INT =f SYS /4011: f INT =f SYS /8100: f INT =f SYS /16101: f INT =f SYS /32110: f INT =f SYS /64111: f INT =f SYS /128To define the TMR active edge of timer/event counter(0=active on low to high;1=active on high to low)To enable/disable timer counting(0=disabled; 1=enabled) 5 Unused bit, read as 067To define the operating mode01=Event count mode (external clock)10=Timer mode (internal clock)11=Pulse width measurement mode00=UnusedTMRC registerInput/output portsThere are 23 bidirectional input/output lines in themicrocontroller, labeled as PA, PB, PC and PD, whichare mapped to the data memory of [12H], [14H], [16H]and [18H] respectively. All of these I/O ports can beused for input and output operations. For input operation,these ports are non-latching, that is, the inputsmust be ready at the T2 rising edge of instruction MOVA,[m] (m=12H, 14H, 16H or 18H). For output operation,all the data is latched and remains unchanged until theoutput latch is rewritten.Each I/O line has its own control register (PAC, PBC,PCC, PDC) to control the input/output configuration.With this control register, CMOS output or schmitt triggerinput with or without pull-high resistor structures canbe reconfigured dynamically (i.e. on-the-fly) under softwarecontrol. To function as an input, the correspondinglatch of the control register must write 1. The inputsource also depends on the control register. If the controlregister bit is 1, the input will read the pad state. Ifthe control register bit is 0, the contents of the latcheswill move to the internal bus. The latter is possible in theread-modify-write instruction.For output function, CMOS is the only configuration.These control registers are mapped to locations 13H,15H, 17H and 19H.After a chip reset, these input/output lines remain at highlevels or floating state (dependent on pull-high options).Each bit of these input/output latches can be set orcleared by SET [m].i and CLR [m].i (m=12H, 14H,16H or 18H) instructions.Some instructions first input data and then follow theoutput operations. For example, SET [m].i, CLR[m].i, CPL [m], CPLA [m] read the entire port statesinto the CPU, execute the defined operations(bit-operation), and then write the results back to thelatches or the accumulator.Each line of port A has the capability of waking-up thedevice. The highest 3-bit of port C and 6-bit of port D arenot physically implemented; on reading them a 0 is returnedwhereas writing then results in a no-operation.See Application note.Each I/O port has a pull-high option. Once the pull-highoption is selected, the I/O port has a pull-high resistor,otherwise, theres none. Take note that a non-pull-highI/O port operating in input mode will cause a floatingstate.The PA3 is pin-shared with the PFD signal. If the PFDoption is selected, the output signal in output mode ofPA3 will be the PFD signal generated by timer/eventcounter overflow signal. The input mode always remainingits original functions. Once the PFD option is selected,the PFD output signal is controlled by PA3 dataregister only. The I/O functions of PA3 are shown below.I/OModePA3Note:I/P(Normal)LogicalInputO/P(Normal)LogicalOutputI/P(PFD)LogicalInputO/P(PFD)PFD(Timer on)The PFD frequency is the timer/event counteroverflowfrequencydividedby2.Rev. 1.40 15 February 8, 2002

HT46R238 , ,, = J= * K I+ JH * EJ, 32 79 HEJA + JH 4 A C EI JA H+ D EF 4 A I A J4 A = @ + JH 4 A C EI JA H9 HEJA , = J= 4 A C EI JA H2 , H2 9 2 ) !2 , H2 9 2 ,+ 35, = J= * EJ, 3+ 357:7: 2 2 %2 , - 2 ) ! 2 ) 2 )2 ) ! 2 ,2 ) " 6 42 ) # 1 62 ) $ 2 ) %2 * ) 2 * % ) %2 + 2 + #2 , 2 9 2 , 2 9 4 A = @ , = J= 4 A C EI JA H5 O I JA 9 = A K F2 ) O 1 6 B H2 ) # O6 4 B H2 ) " OInput/output portsThe PA5 and PA4 are pin-shared with INT and TMR pinsrespectively.The PB can also be used as A/D converter inputs. TheA/D function will be described later. There is a PWMfunction shared with PD0/PD1. If the PWM function isenabled, the PWM0/PWM1 signal will appear onPD0/PD1 (if PD0/PD1 is operating in output mode). TheI/O functions of PD0/PD1 are as shown.I/OModePD0PD1I/P(Normal)LogicalInputO/P(Normal)LogicalOutputI/P(PWM)LogicalInputO/P(PWM)PWM0PWM1It is recommended that unused or not bonded out I/Olines should be set as output pins by software instructionto avoid consuming power under input floating state.PWMThe microcontroller provides 2 channels (6+2)/(7+1)(dependent on options) bits PWM output shared withPD0/PD1. The PWM channels have their data registersdenoted as PWM0 (1AH) and PWM1 (1BH). The frequencysource of the PWM counter comes from f SYS .The PWM registers are two 8-bit registers. The waveformsof PWM outputs are as shown. Once thePD0/PD1 are selected as the PWM outputs and the outputfunction of PD0/PD1 are enabled (PDC.0/PDC.1=0), writing 1 to PD0/PD1 data register will enable thePWM output function and writing 0 will force thePD0/PD1 to stay at 0.A (6+2) bits mode PWM cycle is divided into four modulationcycles (modulation cycle 0~modulation cycle 3).Each modulation cycle has 64 PWM input clock period.In a (6+2) bit PWM function, the contents of the PWMregister is divided into two groups. Group 1 of the PWMregister is denoted by DC which is the value ofPWM.7~PWM.2.The group 2 is denoted by AC which is the value ofPWM.1~PWM.0.In a (6+2) bits mode PWM cycle, the duty cycle of eachmodulation cycle is shown in the table.Parameter AC (0~3) Duty CycleModulation cycle i(i=0~3)i

HT46R23B5 ; 5 2 9 2 9 # $ "# $ " # $ " # $ "# $ "2 9 2 9 $ $ "# $ "# $ "# $ "$ $ "2 9 2 9 $ $ "$ $ "# $ "# $ "$ $ "2 9 !2 9 $ $ "$ $ "$ $ " # $ "$ $ "2 9 @ K = JE F A HE @ $ " B 5 ; 52 9 ? O ? A # $ B5 ; 5(6+2) PWM modeB5 ; 5 2 9 2 9 # &# &# &2 9 2 9 # &# &# &2 9 2 9 # &# &# &2 9 !2 9 # &# &# &2 9 @ K = JE F A HE @ & B 5 ; 52 9 ? O ? A # $ B5 ; 5(7+1) PWM modeIn a (7+1) bits mode PWM cycle, the duty cycle of eachmodulation cycle is shown in the table.Parameter AC (0~1) Duty CycleModulation cycle i(i=0~1)i

HT46R23converter circuit is power on. The EOC bit (bit6 of theADCR) is end of A/D conversion flag. Check this bit toknow when A/D conversion is completed. The STARTbit of the ADCR is used to begin the conversion of theA/D converter. Giving START bit a rising edge and fallingedge means that the A/D conversion has started. Inorder to ensure the A/D conversion is completed, theSTART should remain at 0 until the EOC is cleared to0 (end of A/D conversion).The bit 7 of the ACSR is used for testing purposes only.It can not be used by the users. The bit1 and bit0 of theACSR are used to select A/D clock sources.Label(ACSR)ADCS0ADCS1Bits01FunctionSelects the A/D converter clocksource00= system clock201= system clock810= system clock3211= undefined2~6 Unused bit, read as 0TEST 7 For test mode used onlyACSR registerACS2 ACS1 ACS0 Analog Channel0 0 0 A00 0 1 A10 1 0 A20 1 1 A31 0 0 A41 0 1 A51 1 0 A61 1 1 A7Analog input channel selectionWhen the A/D conversion is completed, the A/D interruptrequest flag is set. The EOC bit is set to 1 whenthe START bit is set from 0 to 1.RegisterBit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0ADRL D1 D0 ADRH D9 D8 D7 D6 D5 D4 D3 D2Note: *: D0~D9 is A/D conversion result data bitLSB~MSB.Label(ADCR)BitsFunctionACS0ACS1ACS2PCR0PCR1PCR2012345Defines the analog channel select.Defines the port B configuration select.If PCR0, PCR1 and PCR2 are all zero,the ADC circuit is power off to reducepower consumptionEOC 6START 7Provides response at the end of theA/D conversion.(0= end of A/D conversion)Starts the A/D conversion. (010=start; 01 reset A/D converter)ADCR registerPCR2 PCR1 PCR0 7 6 5 4 3 2 1 00 0 0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB00 0 1 PB7 PB6 PB5 PB4 PB3 PB2 PB1 A00 1 0 PB7 PB6 PB5 PB4 PB3 PB2 A1 A00 1 1 PB7 PB6 PB5 PB4 PB3 A2 A1 A01 0 0 PB7 PB6 PB5 PB4 A3 A2 A1 A01 0 1 PB7 PB6 PB5 A4 A3 A2 A1 A01 1 0 PB7 PB6 A5 A4 A3 A2 A1 A01 1 1 A7 A6 A5 A4 A3 A2 A1 A0Port B configurationRev. 1.40 18 February 8, 2002

HT46R235 6 ) 4 6- + % $ 6 ) , % $ 6 ) ,2 + 4 2 + 4 * * * *) + 5 ) + 5 *2 M A H 4 A I A J * , A BE A 2 * ? BEC K H= JE 5 A A ? J= = C ? D = A ! 5 A A ? J) , + ? ? - N = F A " ? D = A ) B5 ; 5 & 5 J= HJ B) ,? L A HI E 4 A I A J) ,? L A HJA H5 J= HJ B) ,? L A HI E 4 A I A J) ,? L A HJA H- @ B) ,? L A HJA H * : : : *- @ B) ,? L A HJA H ) 2 * E A EI @ EC EJ= E F K J) , ? L A HJA HEI F M A H BBJ HA @ K ? A F M A H? I K F JE JA ) , ? L A HJE C JE A EI % $ 6 ) , : : : * A = I @ J? = HA ) , + ? ? K I J> A B5 ; 5 B5 ; 5 & B5 ; 5 !A/D conversion timingLow voltage reset LVRThe microcontroller provides low voltage reset circuit inorder to monitor the supply voltage of the device. If thesupply voltage of the device is within the range0.9V~3.3V, such as changing a battery, the LVR will automaticallyreset the device internally.The LVR includes the following specifications: The low voltage (0.9V~3.3V) has to remain in theiroriginal state to exceed 1ms. If the low voltage statedoes not exceed 1ms, the LVR will ignore it and do notperform a reset function. The LVR uses the OR function with the external RESsignal to perform chip reset.The relationship between V DD and V LVR is shown below.8 , , 8 2 4# # 8 # # 8! ! 8! 88 8 4 ' 8Note: V OPR is the voltage range for proper chipoperation at 4MHz system clock.8 , ,# # 88 8 4 8 4 , A JA ? J8 J= C A ' 8 84 A I A J5 EC = 4 A I A J H = F A H= JE 4 A I A J Low voltage resetNote:*1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 systemclock pulses before entering the normal operation.*2: Since low voltage state has to be maintained in its original state for over 1ms, therefore after 1ms delay,the device enters the reset mode.Rev. 1.40 19 February 8, 2002

HT46R23I 2 C BUS Serial InterfaceI 2 C BUS is implemented in the device. The I 2 C BUS is abidirectional two-wire lines. The data line and clock lineare implement in SDA pin and SCL pin. The SDA andSCL are NMOS open drain output pin. They must connecta pull-high resistor respectively.Using the I 2 C BUS, the device has two ways to transferdata. One is in slave transmit mode, the other is in slavereceive mode. There are four registers related to I 2 CBUS; HADR([20H]), HCR([21H]), HSR([22H]),HDR([23H]). The HADR register is the slave addresssetting of the device, if the master sends the calling addresswhich match, it means that this device is selected.The HCR is I 2 C BUS control register which defines thedevice enable or disable the I 2 C BUS as a transmitter oras a receiver. The HSR is I 2 C BUS status register, it respondswith the I 2 C BUS status. The HDR is input/outputdata register, data to transmit or receive must be viathe HDR register.The I 2 C BUS control register contains three bits. TheHEN bit define the enable or disable the I 2 C BUS. If thedata wants transfer via I 2 C BUS, this bit must be set.The HTX bit defines whether the I 2 C BUS is in transmitor receive mode. If the device is as a transmitter, this bitmust be set to 1. The TXAK defines the transmit acknowledgesignal, when the device received 8-bit data,the device sends this bit to I 2 C BUS at the 9th clock. Ifthe receiver wants to continue to receive the next data,this bit must be reset to 0 before receiving data.The I 2 C BUS status register contains 5 bits. The HCF bitis reset to 0 when one data byte is being transferred. Ifone data transfer is completed, this bit is set to 1. TheHASS bit is set 1 when the address is match, and theI 2 C BUS interrupt request flag is set to 1. If the interruptis enabled and the stack is not full, a subroutine callto location 10H will occur. Writing data to the I 2 C BUScontrol register clears HAAS bit. If the address is notmatch, this bit is reset to 0. The HBB bit is set to respondthe I 2 C BUS is busy. It mean that a START signalis detected. This bit is reset to 0 when the I 2 C BUS isnot busy. It means that a STOP signal is detected andthe I 2 C BUS is free. The SRW bit defines the read/writecommand bit, if the calling address is match. WhenHAAS is set to 1, the device check SRW bit to determinewhether the device is working in transmit or receivemode. When SRW bit is set 1, it means that themaster wants to read data from I 2 C BUS, the slave devicemust write data to I 2 C BUS, so the slave device isworking in transmit mode. When SRW is reset to 0, itmeans that the master wants to write data to I 2 C BUS,the slave device must read data from the bus, so theslave device is working in receive mode. The RXAK bitis reset 0 indicates an acknowledges signal has beenreceived. In the transmit mode, the transmitter checksRXAK bit to know the receiver which wants to receivethe next data byte, so the transmitter continue to writedata to the I 2 C BUS until the RXAK bit is set to 1 andthe transmitter releases the SDA line, so that the mastercan send the STOP signal to release the bus.The HADR bit7-bit1 define the device slave address. Atthe beginning of transfer, the master must select a deviceby sending the address of the slave device. The bit0 is unused and is not defined. If the I 2 C BUS receives astart signal, all slave device notice the continuity of the8-bit data. The front of 7 bits is slave address and thefirst bit is MSB. If the address is match, the HAAS statusbit is set and generate an I 2 C BUS interrupt. In the ISR,the slave device must check the HAAS bit to know theI 2 C BUS interrupt comes from the slave address thathas match or completed one 8-bit data transfer. The lastbit of the 8-bit data is read/write command bit, it respondsin SRW bit. The slave will check the SRW bit toknow if the master wants to transmit or receive data. Thedevice check SRW bit to know it is as a transmitter or receiver.Bit7~Bit1Slave AddressHADR registerNote: means undefinedBit0The HDR register is the I 2 C BUS input/output data register.Before transmitting data, the HDR must write thedata which we want to transmit. Before receiving data,the device must dummy read data from HDR. Transmitor Receive data from I 2 C BUS must be via the HDR register.At the beginning of the transfer of the I 2 C BUS, thedevice must initial the bus, the following are the notes forinitialing the I 2 C BUS:1: Write the I 2 C BUS address register (HADR) to defineits own slave address.2: Set HEN bit of I 2 C BUS control register (HCR) bit 0 toenable the I 2 C BUS.Label(HCR) BitsFunctionHEN 7To enable/disable I 2 C BUS function(0= disable; 1= enable) 6 Unused bit, read as 0 5 Unused bit, read as 0HTX 4To define the transmit/receive mode(0= receive mode; 1= transmit)TXAK 3To enable/disable transmit acknowledge(0= acknowledge; 1= dont acknowledge)0~2 Unused bit, read as 0HCR registerRev. 1.40 20 February 8, 2002

HT46R233: Set EHI bit of the interrupt control register 1 (INTC1)bit 0 to enable the I 2 C BUS interrupt.Label(HSR)BitsFunctionHCF 7HCF is clear to 0 when one data byte isbeing transferred, HCF is set to 1 indicating8-bit data communication hasbeen finished.HAAS 6HAAS is set to 1 when the calling addressedis matched, and I 2 C BUS interruptwill occur and HIF is set.HBB 5HBB is set to 1 when I 2 C BUS is busyand HBB is cleared to 0 means thatthe I 2 C BUS is not busy. 4 Unused bit, read as 0 3 Unused bit, read as 0SRW 2SRW is set to 1 when the masterwants to read data from the I 2 C BUS, sothe slave must transmit data to the master.SRW is cleared to 0 when themaster wants to write data to the I 2 CBUS, so the slave must receive datafrom the master. 1 Unused bit, read as 0RXAK 0RXAK is cleared to 0 when the masterreceives an 8-bit data and acknowledgmentat the 9th clock, RXAK is set to 1means not acknowledged.HSR registerStart signalThe START signal is generated only by the master device.The other device in the bus must detect the STARTsignal to set the I 2 C BUS busy bit (HBB). The STARTsignal is SDA line from high to low, when SCL is high.Slave addressThe master must select a device for transferring thedata by sending the slave device address after theSTART signal. All device in the I 2 C BUS will receive theI 2 C BUS slave address (7 bits) to compare with its ownslave address (7 bits). If the slave address is matched,the slave device will generate an interrupt and save thefollowing bit (8th bit) to SRW bit and sends an acknowledgebit (low level) to the 9th bit. The slave device alsosets the status flag (HAAS), when the slave address ismatched.In interrupt subroutine, check HAAS bit to know whetherthe I 2 C BUS interrupt comes from a slave address that ismatched or a data byte transfer is completed. When theslave address is matched, the device must be in transmitmode or receive mode and write data to HDR ordummy read from HDR to release the SCL line.SRW bitThe SRW bit means that the master device wants toread from or write to the I 2 C BUS. The slave devicecheck this bit to understand itself if it is a transmitter or areceiver. The SRW bit is set to 1 means that the masterwants to read data from the I 2 C BUS, so the slave de-5 + 5 J= HJ5 4 9 ) + 5 , ) 5 + , = J=) + 5 J F 5 , )5 5 J= HJ > EJ5 ) 5 = L A ) @ @ HA I I % > EJI 5 4 5 4 9 > EJ > EJ 5 = L A @ A L E? A I A @ = ? ? M A @ C A > EJ > EJ, , = J= & > EJI ) ) + 4 : ) > EJB HJH= I EJJA H6 : ) > EJB HHA ? A EL A H > EJ2 5 J F > EJ5 5 ) 5 4 , ) , ) 5 5 ) 5 4 , ) , ) 2Slave addressRev. 1.40 21 February 8, 2002

HT46R23Application Circuits 5 ++ EH? K EJ5 A A > A M 9 9 8 , , 5 + 5 +8 , ,4 - 58 5 50 6 " $ 4 !2 ) 2 )2 ) ! 2 ,2 ) " 6 42 ) # 1 62 ) $ 5 , )2 ) % 5 + 2 + 2 + "2 * ) 2 * % ) %2 , 2 9 2 , 2 9 8 , ," % F 4 5 +B5 ; 5 " 5 + 5 +4 + I O I JA I ? E= J H! 9 4 5 + % # 9+ + 5 + 5 ++ HO I J= I O I JA I ? E= J H+ + ! F EBB5 ; 5 0 JD A HM EI A + + JA 6 D A HA I EI J= ? A = @ ? = F = ? EJ= ? A B HHA I A J? EH? K EJI D K @ > A @ A I EC A @J A I K HA JD = JJD A 8 , , EI I J= > A = @ HA = E I E = L = E@ H= C A BJD A F A H= JE C L J= C A > A B HA > HE C E C 4 - 5 J D EC D Rev. 1.40 26 February 8, 2002

HT46R23Instruction Set SummaryMnemonicArithmeticADD A,[m]ADDM A,[m]ADD A,xADC A,[m]ADCM A,[m]SUB A,xSUB A,[m]SUBM A,[m]SBC A,[m]SBCM A,[m]DAA [m]Logic OperationAND A,[m]OR A,[m]XOR A,[m]ANDM A,[m]ORM A,[m]XORM A,[m]AND A,xOR A,xXOR A,xCPL [m]CPLA [m]Increment & DecrementINCA [m]INC [m]DECA [m]DEC [m]RotateRRA [m]RR [m]RRCA [m]RRC [m]RLA [m]RL [m]RLCA [m]RLC [m]Data MoveMOV A,[m]MOV [m],AMOV A,xBit OperationCLR [m].iSET [m].iDescriptionAdd data memory to ACCAdd ACC to data memoryAdd immediate data to ACCAdd data memory to ACC with carryAdd ACC to data memory with carrySubtract immediate data from ACCSubtract data memory from ACCSubtract data memory from ACC with result in data memorySubtract data memory from ACC with carrySubtract data memory from ACC with carry and result in data memoryDecimal adjust ACC for addition with result in data memoryAND data memory to ACCOR data memory to ACCExclusive-OR data memory to ACCAND ACC to data memoryOR ACC to data memoryExclusive-OR ACC to data memoryAND immediate data to ACCOR immediate data to ACCExclusive-OR immediate data to ACCComplement data memoryComplement data memory with result in ACCIncrement data memory with result in ACCIncrement data memoryDecrement data memory with result in ACCDecrement data memoryRotate data memory right with result in ACCRotate data memory rightRotate data memory right through carry with result in ACCRotate data memory right through carryRotate data memory left with result in ACCRotate data memory leftRotate data memory left through carry with result in ACCRotate data memory left through carryMove data memory to ACCMove ACC to data memoryMove immediate data to ACCClear bit of data memorySet bit of data memoryInstructionCycleFlagAffected1 Z,C,AC,OV1 (1) Z,C,AC,OV1 Z,C,AC,OV1 Z,C,AC,OV1 (1) Z,C,AC,OV1 Z,C,AC,OV1 Z,C,AC,OV1 (1) Z,C,AC,OV1 Z,C,AC,OV1 (1) Z,C,AC,OV1 (1) C1111 (1)1 (1)1 (1)1111 (1)1ZZZZZZZZZZZ1Z1 (1)Z1Z1 (1) Z1 None1 (1) None1C1 (1)C1 None1 (1) None1C1 (1) C11 (1)1NoneNoneNone1 (1) None1 (1) NoneRev. 1.40 27 February 8, 2002

HT46R23MnemonicBranchJMP addrSZ [m]SZA [m]SZ [m].iSNZ [m].iSIZ [m]SDZ [m]SIZA [m]SDZA [m]CALL addrRETRET A,xRETITable ReadTABRDC [m]TABRDL [m]MiscellaneousNOPCLR [m]SET [m]CLR WDTCLR WDT1CLR WDT2SWAP [m]SWAPA [m]HALTDescriptionJump unconditionallySkip if data memory is zeroSkip if data memory is zero with data movement to ACCSkip if bit i of data memory is zeroSkip if bit i of data memory is not zeroSkip if increment data memory is zeroSkip if decrement data memory is zeroSkip if increment data memory is zero with result in ACCSkip if decrement data memory is zero with result in ACCSubroutine callReturn from subroutineReturn from subroutine and load immediate data to ACCReturn from interruptRead ROM code (current page) to data memory and TBLHRead ROM code (last page) to data memory and TBLHNo operationClear data memorySet data memoryClear Watchdog TimerPre-clear Watchdog TimerPre-clear Watchdog TimerSwap nibbles of data memorySwap nibbles of data memory with result in ACCEnter power down modeInstructionCycle21 (2)1 (2)1 (2)1 (2)1 (3)1 (3)1 (2)1 (2)2222FlagAffectedNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNone2 (1) None2 (1) None11 (1)1 (1)1111 (1)11NoneNoneNoneTO,PDTO (4) ,PD (4)TO (4) ,PD (4)NoneNoneTO,PDNote:x: Immediate datam: Data memory addressA: Accumulatori: 0~7 number of bitsaddr: Program memory address: Flag is affected: Flag is not affected(1) : If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle(four system clocks).(2) : If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one morecycle (four system clocks). Otherwise the original instruction cycle is unchanged.(3) : (1) and (2)(4) : The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing theCLR WDT1 or CLR WDT2 instruction, the TO and PD are cleared.Otherwise the TO and PD flags remain unchanged.Rev. 1.40 28 February 8, 2002

HT46R23Instruction DefinitionADC A,[m]DescriptionOperationAffected flag(s)Add data memory and carry to the accumulatorThe contents of the specified data memory, accumulator and the carry flag are added simultaneously,leaving the result in the accumulator.ACC ACC+[m]+CTC2 TC1 TO PD OV Z AC C ADCM A,[m]DescriptionOperationAffected flag(s)Add the accumulator and carry to data memoryThe contents of the specified data memory, accumulator and the carry flag are added simultaneously,leaving the result in the specified data memory.[m] ACC+[m]+CTC2 TC1 TO PD OV Z AC C ADD A,[m]DescriptionOperationAffected flag(s)Add data memory to the accumulatorThe contents of the specified data memory and the accumulator are added. The result isstored in the accumulator.ACC ACC+[m]TC2 TC1 TO PD OV Z AC C ADD A,xDescriptionOperationAffected flag(s)Add immediate data to the accumulatorThe contents of the accumulator and the specified data are added, leaving the result in the accumulator.ACC ACC+xTC2 TC1 TO PD OV Z AC C ADDM A,[m]DescriptionOperationAffected flag(s)Add the accumulator to the data memoryThe contents of the specified data memory and the accumulator are added. The result isstored in the data memory.[m] ACC+[m]TC2 TC1 TO PD OV Z AC C Rev. 1.40 29 February 8, 2002

HT46R23AND A,[m]DescriptionOperationAffected flag(s)Logical AND accumulator with data memoryData in the accumulator and the specified data memory perform a bitwise logical_AND operation.The result is stored in the accumulator.ACC ACC AND [m]TC2 TC1 TO PD OV Z AC C AND A,xDescriptionOperationAffected flag(s)Logical AND immediate data to the accumulatorData in the accumulator and the specified data perform a bitwise logical_AND operation. Theresult is stored in the accumulator.ACC ACC AND xTC2 TC1 TO PD OV Z AC C ANDM A,[m]DescriptionOperationAffected flag(s)Logical AND data memory with the accumulatorData in the specified data memory and the accumulator perform a bitwise logical_AND operation.The result is stored in the data memory.[m] ACC AND [m]TC2 TC1 TO PD OV Z AC C CALL addrDescriptionOperationAffected flag(s)Subroutine callThe instruction unconditionally calls a subroutine located at the indicated address. The programcounter increments once to obtain the address of the next instruction, and pushes thisonto the stack. The indicated address is then loaded. Program execution continues with theinstruction at this address.Stack PC+1PC addrTC2 TC1 TO PD OV Z AC C CLR [m]Clear data memoryDescription The contents of the specified data memory are cleared to 0.OperationAffected flag(s)[m] 00HTC2 TC1 TO PD OV Z AC C Rev. 1.40 30 February 8, 2002

HT46R23CLR [m].iClear bit of data memoryDescription The bit i of the specified data memory is cleared to 0.Operation [m].i 0Affected flag(s)TC2 TC1 TO PD OV Z AC C CLR WDTDescriptionOperationAffected flag(s)Clear Watchdog TimerThe WDT and the WDT Prescaler are cleared (re-counting from 0). The power down bit (PD)and time-out bit (TO) are cleared.WDT and WDT Prescaler 00HPD and TO 0TC2 TC1 TO PD OV Z AC C 0 0 CLR WDT1DescriptionPreclear Watchdog TimerThe TO, PD flags, WDT and the WDT Prescaler has cleared (re-counting from 0), if the otherpreclear WDT instruction has been executed. Only execution of this instruction without theother preclear instruction just sets the indicated flag which implies this instruction has beenexecuted and the TO and PD flags remain unchanged.Operation WDT and WDT Prescaler 00H*PD and TO 0*Affected flag(s)TC2 TC1 TO PD OV Z AC C 0* 0* CLR WDT2DescriptionPreclear Watchdog TimerThe TO, PD flags, WDT and the WDT Prescaler are cleared (re-counting from 0), if the otherpreclear WDT instruction has been executed. Only execution of this instruction without theother preclear instruction, sets the indicated flag which implies this instruction has been executedand the TO and PD flags remain unchanged.Operation WDT and WDT Prescaler 00H*PD and TO 0*Affected flag(s)TC2 TC1 TO PD OV Z AC C 0* 0* CPL [m]DescriptionOperationAffected flag(s)Complement data memoryEach bit of the specified data memory is logically complemented (1s complement). Bits whichpreviously contained a 1 are changed to 0 and vice-versa.[m] [m]TC2 TC1 TO PD OV Z AC C Rev. 1.40 31 February 8, 2002

HT46R23CPLA [m]DescriptionOperationAffected flag(s)Complement data memory and place result in the accumulatorEach bit of the specified data memory is logically complemented (1s complement). Bits whichpreviously contained a 1 are changed to 0 and vice-versa. The complemented result is storedin the accumulator and the contents of the data memory remain unchanged.ACC [m]TC2 TC1 TO PD OV Z AC C DAA [m]DescriptionOperationAffected flag(s)Decimal-Adjust accumulator for additionThe accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulatoris divided into two nibbles. Each nibble is adjusted to the BCD code and an internal carry(AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustmentis done by adding 6 to the original value if the original value is greater than 9 or a carry (AC orC) is set; otherwise the original value remains unchanged. The result is stored in the datamemory and only the carry flag (C) may be affected.If ACC.3~ACC.0 >9 or AC=1then [m].3~[m].0 (ACC.3~ACC.0)+6, AC1=ACelse [m].3~[m].0 (ACC.3~ACC.0), AC1=0andIf ACC.7~ACC.4+AC1 >9 or C=1then [m].7~[m].4 ACC.7~ACC.4+6+AC1,C=1else [m].7~[m].4 ACC.7~ACC.4+AC1,C=CTC2 TC1 TO PD OV Z AC C DEC [m]Decrement data memoryDescription Data in the specified data memory is decremented by 1.OperationAffected flag(s)[m] [m]1TC2 TC1 TO PD OV Z AC C DECA [m]DescriptionOperationAffected flag(s)Decrement data memory and place result in the accumulatorData in the specified data memory is decremented by 1, leaving the result in the accumulator.The contents of the data memory remain unchanged.ACC [m]1TC2 TC1 TO PD OV Z AC C Rev. 1.40 32 February 8, 2002

HT46R23HALTDescriptionOperationAffected flag(s)Enter power down modeThis instruction stops program execution and turns off the system clock. The contents of theRAM and registers are retained. The WDT and prescaler are cleared. The power down bit(PD) is set and the WDT time-out bit (TO) is cleared.PC PC+1PD 1TO 0TC2 TC1 TO PD OV Z AC C 0 1 INC [m]Increment data memoryDescription Data in the specified data memory is incremented by 1OperationAffected flag(s)[m] [m]+1TC2 TC1 TO PD OV Z AC C INCA [m]DescriptionOperationAffected flag(s)Increment data memory and place result in the accumulatorData in the specified data memory is incremented by 1, leaving the result in the accumulator.The contents of the data memory remain unchanged.ACC [m]+1TC2 TC1 TO PD OV Z AC C JMP addrDescriptionOperationAffected flag(s)Directly jumpThe program counter are replaced with the directly-specified address unconditionally, andcontrol is passed to this destination.PC addrTC2 TC1 TO PD OV Z AC C MOV A,[m]DescriptionOperationAffected flag(s)Move data memory to the accumulatorThe contents of the specified data memory are copied to the accumulator.ACC [m]TC2 TC1 TO PD OV Z AC C Rev. 1.40 33 February 8, 2002

HT46R23MOV A,xDescriptionOperationAffected flag(s)Move immediate data to the accumulatorThe 8-bit data specified by the code is loaded into the accumulator.ACC xTC2 TC1 TO PD OV Z AC C MOV [m],ADescriptionOperationAffected flag(s)Move the accumulator to data memoryThe contents of the accumulator are copied to the specified data memory (one of the datamemories).[m] ACCTC2 TC1 TO PD OV Z AC C NOPDescriptionOperationAffected flag(s)No operationNo operation is performed. Execution continues with the next instruction.PC PC+1TC2 TC1 TO PD OV Z AC C OR A,[m]DescriptionOperationAffected flag(s)Logical OR accumulator with data memoryData in the accumulator and the specified data memory (one of the data memories) perform abitwise logical_OR operation. The result is stored in the accumulator.ACC ACC OR [m]TC2 TC1 TO PD OV Z AC C OR A,xDescriptionOperationAffected flag(s)Logical OR immediate data to the accumulatorData in the accumulator and the specified data perform a bitwise logical_OR operation. Theresult is stored in the accumulator.ACC ACC OR xTC2 TC1 TO PD OV Z AC C ORM A,[m]DescriptionOperationAffected flag(s)Logical OR data memory with the accumulatorData in the data memory (one of the data memories) and the accumulator perform a bitwiselogical_OR operation. The result is stored in the data memory.[m] ACC OR [m]TC2 TC1 TO PD OV Z AC C Rev. 1.40 34 February 8, 2002

HT46R23RETDescriptionOperationAffected flag(s)Return from subroutineThe program counter is restored from the stack. This is a 2-cycle instruction.PC StackTC2 TC1 TO PD OV Z AC C RET A,xDescriptionOperationAffected flag(s)Return and place immediate data in the accumulatorThe program counter is restored from the stack and the accumulator loaded with the specified8-bit immediate data.PC StackACC xTC2 TC1 TO PD OV Z AC C RETIDescriptionOperationAffected flag(s)Return from interruptThe program counter is restored from the stack, and interrupts are enabled by setting the EMIbit. EMI is the enable master (global) interrupt bit.PC StackEMI 1TC2 TC1 TO PD OV Z AC C RL [m]Rotate data memory leftDescription The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.OperationAffected flag(s)[m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6)[m].0 [m].7TC2 TC1 TO PD OV Z AC C RLA [m]DescriptionOperationAffected flag(s)Rotate data memory left and place result in the accumulatorData in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotatedresult in the accumulator. The contents of the data memory remain unchanged.ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6)ACC.0 [m].7TC2 TC1 TO PD OV Z AC C Rev. 1.40 35 February 8, 2002

HT46R23RLC [m]DescriptionOperationAffected flag(s)Rotate data memory left through carryThe contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replacesthe carry bit; the original carry flag is rotated into the bit 0 position.[m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6)[m].0 CC [m].7TC2 TC1 TO PD OV Z AC C RLCA [m]DescriptionOperationAffected flag(s)Rotate left through carry and place result in the accumulatorData in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces thecarry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored inthe accumulator but the contents of the data memory remain unchanged.ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6)ACC.0 CC [m].7TC2 TC1 TO PD OV Z AC C RR [m]Rotate data memory rightDescription The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7.OperationAffected flag(s)[m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6)[m].7 [m].0TC2 TC1 TO PD OV Z AC C RRA [m]DescriptionOperationAffected flag(s)Rotate right and place result in the accumulatorData in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving therotated result in the accumulator. The contents of the data memory remain unchanged.ACC.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6)ACC.7 [m].0TC2 TC1 TO PD OV Z AC C RRC [m]DescriptionOperationAffected flag(s)Rotate data memory right through carryThe contents of the specified data memory and the carry flag are together rotated 1 bit right.Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.[m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6)[m].7 CC [m].0TC2 TC1 TO PD OV Z AC C Rev. 1.40 36 February 8, 2002

HT46R23RRCA [m]DescriptionOperationAffected flag(s)Rotate right through carry and place result in the accumulatorData of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces thecarry bit and the original carry flag is rotated into the bit 7 position. The rotated result is storedin the accumulator. The contents of the data memory remain unchanged.ACC.i [m].(i+1); [m].i:bit i of the data memory (i=0~6)ACC.7 CC [m].0TC2 TC1 TO PD OV Z AC C SBC A,[m]DescriptionOperationAffected flag(s)Subtract data memory and carry from the accumulatorThe contents of the specified data memory and the complement of the carry flag are subtractedfrom the accumulator, leaving the result in the accumulator.ACC ACC+[m]+CTC2 TC1 TO PD OV Z AC C SBCM A,[m]DescriptionOperationAffected flag(s)Subtract data memory and carry from the accumulatorThe contents of the specified data memory and the complement of the carry flag are subtractedfrom the accumulator, leaving the result in the data memory.[m] ACC+[m]+CTC2 TC1 TO PD OV Z AC C SDZ [m] Skip if decrement data memory is 0DescriptionOperationAffected flag(s)The contents of the specified data memory are decremented by 1. If the result is 0, the next instructionis skipped. If the result is 0, the following instruction, fetched during the current instructionexecution, is discarded and a dummy cycle is replaced to get the proper instruction(2 cycles). Otherwise proceed with the next instruction (1 cycle).Skip if ([m]1)=0, [m] ([m]1)TC2 TC1 TO PD OV Z AC C SDZA [m] Decrement data memory and place result in ACC, skip if 0DescriptionOperationAffected flag(s)The contents of the specified data memory are decremented by 1. If the result is 0, the next instructionis skipped. The result is stored in the accumulator but the data memory remains unchanged.If the result is 0, the following instruction, fetched during the current instructionexecution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles).Otherwise proceed with the next instruction (1 cycle).Skip if ([m]1)=0, ACC ([m]1)TC2 TC1 TO PD OV Z AC C Rev. 1.40 37 February 8, 2002

HT46R23SET [m]Set data memoryDescription Each bit of the specified data memory is set to 1.Operation[m] FFHAffected flag(s)TC2 TC1 TO PD OV Z AC C SET [m]. iSet bit of data memoryDescription Bit i of the specified data memory is set to 1.Operation [m].i 1Affected flag(s)TC2 TC1 TO PD OV Z AC C SIZ [m] Skip if increment data memory is 0DescriptionThe contents of the specified data memory are incremented by 1. If the result is 0, the followinginstruction, fetched during the current instruction execution, is discarded and a dummy cycleis replaced to get the proper instruction (2 cycles). Otherwise proceed with the nextinstruction (1 cycle).OperationSkip if ([m]+1)=0, [m] ([m]+1)Affected flag(s)TC2 TC1 TO PD OV Z AC C SIZA [m] Increment data memory and place result in ACC, skip if 0DescriptionThe contents of the specified data memory are incremented by 1. If the result is 0, the next instructionis skipped and the result is stored in the accumulator. The data memory remains unchanged.If the result is 0, the following instruction, fetched during the current instructionexecution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles).Otherwise proceed with the next instruction (1 cycle).OperationSkip if ([m]+1)=0, ACC ([m]+1)Affected flag(s)TC2 TC1 TO PD OV Z AC C SNZ [m].i Skip if bit i of the data memory is not 0DescriptionIf bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the datamemory is not 0, the following instruction, fetched during the current instruction execution, isdiscarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwiseproceed with the next instruction (1 cycle).OperationSkip if [m].i0Affected flag(s)TC2 TC1 TO PD OV Z AC C Rev. 1.40 38 February 8, 2002

HT46R23SUB A,[m]DescriptionOperationAffected flag(s)Subtract data memory from the accumulatorThe specified data memory is subtracted from the contents of the accumulator, leaving the resultin the accumulator.ACC ACC+[m]+1TC2 TC1 TO PD OV Z AC C SUBM A,[m]DescriptionOperationAffected flag(s)Subtract data memory from the accumulatorThe specified data memory is subtracted from the contents of the accumulator, leaving the resultin the data memory.[m] ACC+[m]+1TC2 TC1 TO PD OV Z AC C SUB A,xDescriptionOperationAffected flag(s)Subtract immediate data from the accumulatorThe immediate data specified by the code is subtracted from the contents of the accumulator,leaving the result in the accumulator.ACC ACC+x+1TC2 TC1 TO PD OV Z AC C SWAP [m]DescriptionOperationAffected flag(s)Swap nibbles within the data memoryThe low-order and high-order nibbles of the specified data memory (1 of the data memories)are interchanged.[m].3~[m].0 [m].7~[m].4TC2 TC1 TO PD OV Z AC C SWAPA [m]DescriptionOperationAffected flag(s)Swap data memory and place result in the accumulatorThe low-order and high-order nibbles of the specified data memory are interchanged, writingthe result to the accumulator. The contents of the data memory remain unchanged.ACC.3~ACC.0 [m].7~[m].4ACC.7~ACC.4 [m].3~[m].0TC2 TC1 TO PD OV Z AC C Rev. 1.40 39 February 8, 2002

HT46R23SZ [m] Skip if data memory is 0DescriptionOperationIf the contents of the specified data memory are 0, the following instruction, fetched during thecurrent instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction(2 cycles). Otherwise proceed with the next instruction (1 cycle).Skip if [m]=0Affected flag(s)TC2 TC1 TO PD OV Z AC C SZA [m] Move data memory to ACC, skip if 0Description The contents of the specified data memory are copied to the accumulator. If the contents is 0,the following instruction, fetched during the current instruction execution, is discarded and adummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with thenext instruction (1 cycle).OperationSkip if [m]=0Affected flag(s)TC2 TC1 TO PD OV Z AC C SZ [m].i Skip if bit i of the data memory is 0DescriptionOperationIf bit i of the specified data memory is 0, the following instruction, fetched during the current instructionexecution, is discarded and a dummy cycle is replaced to get the proper instruction(2 cycles). Otherwise proceed with the next instruction (1 cycle).Skip if [m].i=0Affected flag(s)TC2 TC1 TO PD OV Z AC C TABRDC [m]DescriptionOperationAffected flag(s)Move the ROM code (current page) to TBLH and data memoryThe low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved tothe specified data memory and the high byte transferred to TBLH directly.[m] ROM code (low byte)TBLH ROM code (high byte)TC2 TC1 TO PD OV Z AC C TABRDL [m]DescriptionOperationAffected flag(s)Move the ROM code (last page) to TBLH and data memoryThe low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to thedata memory and the high byte transferred to TBLH directly.[m] ROM code (low byte)TBLH code (high byte)TC2 TC1 TO PD OV Z AC C Rev. 1.40 40 February 8, 2002

HT46R23XOR A,[m]DescriptionOperationAffected flag(s)Logical XOR accumulator with data memoryData in the accumulator and the indicated data memory perform a bitwise logical Exclusive_ORoperation and the result is stored in the accumulator.ACC ACC XOR [m]TC2 TC1 TO PD OV Z AC C XORM A,[m]DescriptionOperationAffected flag(s)Logical XOR data memory with the accumulatorData in the indicated data memory and the accumulator perform a bitwise logical Exclusive_ORoperation. The result is stored in the data memory. The 0 flag is affected.[m] ACC XOR [m]TC2 TC1 TO PD OV Z AC C XOR A,xDescriptionOperationAffected flag(s)Logical XOR immediate data to the accumulatorData in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation.The result is stored in the accumulator. The 0 flag is affected.ACC ACC XOR xTC2 TC1 TO PD OV Z AC C Rev. 1.40 41 February 8, 2002

HT46R23Holtek Semiconductor Inc. (Headquarters)No.3, Creation Rd. II, Science-based Industrial Park, Hsinchu, TaiwanTel: 886-3-563-1999Fax: 886-3-563-1189http://www.holtek.com.twHoltek Semiconductor Inc. (Sales Office)11F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, TaiwanTel: 886-2-2782-9635Fax: 886-2-2782-9636Fax: 886-2-2782-7128 (International sales hotline)Holtek Semiconductor (Hong Kong) Ltd.RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong KongTel: 852-2-745-8288Fax: 852-2-742-8657Holtek Semiconductor (Shanghai) Inc.7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, ChinaTel: 021-6485-5560Fax: 021-6485-0313http://www.holtek.com.cnHolmate Semiconductor, Inc.48531 Warm Springs Boulevard, Suite 413, Fremont, CA 94539Tel: 510-252-9880Fax: 510-252-9885http://www.holmate.comCopyright 2002 by HOLTEK SEMICONDUCTOR INC.The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumesno responsibility arising from the use of the specifications described. The applications mentioned herein are usedsolely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitablewithout further modification, nor recommends the use of its products for application that may present a risk to human lifedue to malfunction or otherwise. Holtek reserves the right to alter its products without prior notification. For the mostup-to-date information, please visit our web site at http://www.holtek.com.tw.Rev. 1.40 42 February 8, 2002