COPYRIGHT 2008, PRINCETON UNIVERSITY PRESS

high-performance computing hardware 357TABLE 14.1Computation of c =(a + b)/(d ∗ f)Arithmetic Unit Step 1 Step 2 Step 3 Step 4A1 Fetch a Fetch b Add —A2 Fetch d Fetch f Multiply —A3 — — — Divide14.3 The Central Processing UnitHow does the CPU get to be so fast? Often, it employs prefetching and pipelining;that is, it has the ability to prepare for the next instruction before the current one hasfinished. It is like an assembly line or a bucket brigade in which the person fillingthe buckets at one end of the line does not wait for each bucket to arrive at the otherend before filling another bucket. In the same way a processor fetches, reads, anddecodes an instruction while another instruction is executing. Consequently, eventhough it may take more than one cycle to perform some operations, it is possiblefor data to be entering and leaving the CPU on each cycle. To illustrate, Table 14.1indicates how the operation c =(a + b)/(d ∗ f) is handled. Here the pipelined arithmeticunits A1 and A2 are simultaneously doing their jobs of fetching and operatingon operands, yet arithmetic unit A3 must wait for the first two units to completetheir tasks before it has something to do (during which time the other two sit idle).14.4 CPU Design: Reduced Instruction Set ComputerReduced instruction set computer (RISC) architecture (also called superscalar) isadesign philosophy for CPUs developed for high-performance computers and nowused broadly. It increases the arithmetic speed of the CPU by decreasing thenumber of instructions the CPU must follow. To understand RISC we contrast itwith complex instruction set computer (CISC), architecture. In the late 1970s, processordesigners began to take advantage of very-large-scale integration (VLSI) whichallowed the placement of hundreds of thousands of devices on a single CPUchip. Much of the space on these early chips was dedicated to microcode programswritten by chip designers and containing machine language instructions that setthe operating characteristics of the computer. There were more than 1000 instructionsavailable, and many were similar to higher-level programming languageslike Pascal and Forth. The price paid for the large number of complex instructionswas slow speed, with a typical instruction taking more than 10 clock cycles. Furthermore,a 1975 study by Alexander and Wortman of the XLP compiler of the IBMSystem/360 showed that about 30 low-level instructions accounted for 99% of theuse with only 10 of these instructions accounting for 80% of the use.The RISC philosophy is to have just a small number of instructions availableat the chip level but to have the regular programmer’s high level-language, such−101COPYRIGHT 2008, PRINCET O N UNIVE R S I T Y P R E S SEVALUATION COPY ONLY. NOT FOR USE IN COURSES.ALLpup_06.04 — 2008/2/15 — Page 357