COPYRIGHT 2008, PRINCETON UNIVERSITY PRESS

358 chapter 14as Fortran or C, translate them into efficient machine instructions for a particularcomputer’s architecture. This simpler scheme is cheaper to design and produce,lets the processor run faster, and uses the space saved on the chip by cutting downon microcode to increase arithmetic power. Specifically, RISC increases the numberof internal CPU registers, thus making it possible to obtain longer pipelines (cache)for the data flow, a significantly lower probability of memory conflict, and someinstruction-level parallelism.The theory behind this philosophy for RISC design is the simple equationdescribing the execution time of a program:CPU time = no.instructions × cycles/instruction × cycle time. (14.1)Here “CPU time” is the time required by a program, “no. instructions” is the totalnumber of machine-level instructions the program requires (sometimes called thepath length), “cycles/instruction” is the number of CPU clock cycles each instructionrequires, and “cycle time” is the actual time it takes for one CPU cycle. Afterviewing (14.1) we can understand the CISC philosophy, which tries to reduce CPUtime by reducing no. instructions, as well as the RISC philosophy, which tries toreduce CPU time by reducing cycles/instruction (preferably to one). For RISC toachieve an increase in performance requires a greater decrease in cycle time andcycles/instruction than the increase in the number of instructions.In summary, the elements of RISC are the following.Single-cycle execution for most machine-level instructions.Small instruction set of less than 100 instructions.Register-based instructions operating on values in registers, with memoryaccess confined to load and store to and from registers.Many registers, usually more than 32.Pipelining, that is, concurrent processing of several instructions.High-level compilers to improve performance.14.5 CPU Design: Multiple-Core ProcessorsThe year preceding the publication of this book has seen a rapid increase in theinclusion of dual-core, or even quad-core, chips as the computational engine ofcomputers. As seen in Figure 14.5, a dual-core chip has two CPUs in one integratedcircuit with a shared interconnect and a shared level-2 cache. This type of configurationwith two or more identical processors connected to a single shared mainmemory is called symmetric multiprocessing, or SMP. It is likely that by the time youread this book, 16-core or greater chips will be available.Although multicore chips were designed for game playing and single precision,they should also be useful in scientific computing if new tools, algorithms, andprogramming methods are employed. These chips attain more speed with lessheat and more energy efficiency than single-core chips, whose heat generationlimits them to clock speeds of less than 4 GHz. In contrast to multiple single-core−101COPYRIGHT 2008, PRINCET O N UNIVE R S I T Y P R E S SEVALUATION COPY ONLY. NOT FOR USE IN COURSES.ALLpup_06.04 — 2008/2/15 — Page 358