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FPGA Design in VHDL - ALSE

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What is a “Complex” <strong>FPGA</strong> ?<br />

Note : Complex ≠ Dense :<br />

• A 1 Meg gates <strong>FPGA</strong> may be very simple to design...<br />

Some aggravat<strong>in</strong>g factors :<br />

• Asynchronism !<br />

• Poor specs...<br />

• External Environment complex or without model.<br />

• Close to Technological Limits.<br />

• Complex algorithms with<strong>in</strong> few clock cycles.<br />

H<strong>in</strong>t : look at the Test Plan.<br />

© Bert CUZEAU - <strong>ALSE</strong> - http://www.alse-fr.com

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