FPGA Design in VHDL - ALSE

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Simulation is the Key Advanced Functional Simulation is one Key to success : • Shorten, secure and simplify the validation phase. • Allow for non-regression tests • Simplify the delivery and acceptance phase. A clever simulation methodology can have an incredible impact (3 x gains are common). => delays & costs can easily be divided by 2 ! © Bert CUZEAU - ALSE - http://www.alse-fr.com
Speeding up the Validation phase Very simple Techniques can dramatically improve the Simulation efficiency, like : • Automation (GUI → Scripts), • Test benches should be self-testing & regressionable, • Don’t eyeball waveforms, • Use extensively File I/O, • Use “on-the-fly” comparison, • Implement interactive tests, ... © Bert CUZEAU - ALSE - http://www.alse-fr.com
Page 1 and 2: © ALSE France - Sept 2001 Designin
Page 3 and 4: Silicon FPGA, ASIC,... Ground for S
Page 5: Test ! Time to Design ! Morale : Co
Page 9 and 10: Example : VHDL Code Generator in
Page 11 and 12: Take advantage of the Silicon You m
Page 13 and 14: Conclusion Today more than ever, su
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FPGA Design in VHDL - ALSE

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