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System-level test Benches<br />
& Verification Tools<br />
<strong>Design</strong> Documentation<br />
Data Management<br />
Quality Management<br />
Know-how Transfer<br />
<strong>FPGA</strong> <strong>Design</strong> Flow<br />
System Analysis & Partition<strong>in</strong>g<br />
Functional Blocks (from Top-Level down)<br />
Unitary RTL Cod<strong>in</strong>g Unitary Synthesis<br />
Unitary Test Bench<br />
Functional Verification<br />
Unitary Validation<br />
System-level Verification<br />
System-Level Synthesis<br />
Place & Route<br />
Post-Layout Simulation<br />
Hardware Validation + F<strong>in</strong>al delivery<br />
© Bert CUZEAU - <strong>ALSE</strong> - http://www.alse-fr.com<br />
Project Management<br />
Méthodology<br />
Guide<br />
<strong>Design</strong> reviews<br />
“Peer Reviews”...<br />
NB : Iterations are not<br />
represented <strong>in</strong> this<br />
simplified diagram
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