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Passive, active, and digital filters (3ed., CRC, 2009) - tiera.ru

Passive, active, and digital filters (3ed., CRC, 2009) - tiera.ru

Passive, active, and digital filters (3ed., CRC, 2009) - tiera.ru

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17-20 <strong>Passive</strong>, Active, <strong>and</strong> Digital Filters1612Switch resistance (×100 K)8400.00 0.05 0.10 0.15 0.20 0.25V in (v)FIGURE 17.15Typical switch resistance for an NMOS transistor.φ΄2V DDφ 1CM V C 38yC pφ 1φ 2M 4 M 3V oφ 1C 1 C Loadφ΄2V OLoadM 7 V xφ 1C 2φ΄2M 6 M 5V SSM 2 M 1V DD(a)φ 2φ 1V SS(b)V SSFIGURE 17.16Voltage doubler. (a) Simplified diagram <strong>and</strong> (b) transistor level diagram.beginning of f 2 , the voltage at the top plate of C 1 is equal to 2V DD V SS . After several clockcycles, if C LOAD is not further discharged, the charge is recombined leading to an output voltage equalto 2V DD – V SS . A practical implementation for an N-well process is shown in Figure 17.16b.In this circuit, the transistors M 1 ,M 2 ,M 3 , <strong>and</strong> M 4 behave as the switches S 1 ,S 2 ,S 3 , <strong>and</strong> S 4 respectively,of Figure 17.16a. While for M 1 <strong>and</strong> M 2 the normal clocks are used, special clock phases are generated forM 3 <strong>and</strong> M 4 because they drive higher voltages. The circuit operates as follows.

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