Passive, active, and digital filters (3ed., CRC, 2009) - tiera.ru

VLSI Implementation of Digital Filters 21-3Program anddata RAMProgramcacheROMProgram addressProgram data busData addressData data busMultiplyArithmetic logicunit (ALU)AccumulateShiftsDMAcontrollerTimerI/OportsPeripheralbusFIGURE 21.1Texas Instruments TMS320C30 architecture.recent examples of the TI family are the TMS320C67x DSP chips (TI, 2006a), and more recent AnalogDevices parts are the ADSP-2116x SHARC chips (Analog Devices, 2006).The architecture of the TI TMS320C30 is illustrated in Figure 21.1. The floating-point word size usedby this processor was 32 bits. The most prominent feature of this chip was the floating-point arithmeticunit, which contains a floating-point multiplier and adder. This unit was highly pipelined to support highthroughput, at the cost of latency; when data is input to the multiplier, for example, the results will notappear on the output from that unit until several clock cycles later. Other features included a separateinteger unit for control calculations, and significant amounts (2k words) of SRAM for data and on-chipinstruction memory. On-chip ROM (4k words) was also optionally provided in order to eliminate theneed for an external boot ROM in some applications. This chip also included a 64-word instruction cacheto allow its use with lower speed memories. The modified Harvard architecture, that is, the separate dataand instruction buses, provided for concurrent instruction and data word transfers within one cycle time.The TMS320C30 offered instruction cycle times as low as 60 ns. A code segment which implementsportions of an finite impulse response (FIR) filter on this device wasRPTS RCMPYF3 *AR0þþ(1),*AR1þþ(1)%,R0jj ADDF3 R0,R2,R2ADDF R0,R2,R0where the MPYF3 instruction performs a pipelined multiply operation in parallel with data andcoefficient pointer increments. The ADDF3 instruction is performed in parallel with the MPYF3instruction, as denoted by the ‘‘jj’’ symbol. Because these operations are in parallel, only one instructioncycle per tap is required. An FIR filter tap was benchmarked at 60 ns on this chip. Similarly, a typicalbiquad infinite impulse response (IIR) filter code segment wasMPYF3MPYF3MPYF3*AR0,*AR1,R0*þþAR0(1),*AR1––(1)%,R1*þþAR0(1),*AR1,R0