The C11 and C++11 Concurrency Model

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ultimately faulty specification (see Section 5.10.3). In this chapter we explain the problem
as precisely as possible, we show that the restriction of thin-air values in C/C++11
invalidates the accepted implementations of atomic accesses, and we explore alternative
solutions, making some concrete suggestions.
5.10.1 Thin-air values, informally
Precisely defining thin-air values is the very problem that the language faces, so instead
of a definition of the term, this chapter offers a series of examples that explore the design
space for the memory model’s restriction of thin-air values. Before the first example of an
execution with a thin-air value, recall the load-buffering test, repeated below. The model
allows the read in each thread to read from the write in the other, completing a cycle in
sb union rf. This behaviour is not only allowed by the C/C++11 memory model, it is
also permitted for analogous programs on both the ARM and IBM Power architectures,
and observable on ARM processors. If load buffering were forbidden by the language, the
lightweight implementations of relaxed accesses would have to be strengthened for Power
and ARM.
int main() {
atomic_int x = 0;
atomic_int y = 0;
{{{ { r1 = x.load(relaxed);
y.store(1,relaxed); }
||| { r2 = y.load(relaxed);
x.store(1,relaxed); }
}}}
return 0;
}
c:R RLX x=1 e:R RLX y=1
sb sb
rf rf
d:W RLX y=1 f:W RLX x=1
Allowed by Power and ARM architectures, and observed on ARM,
so C/C++11 should allow this.
Many of the examples of thin-air values in this section will, at their core, contain
the cyclic shape of this load-buffering execution. The first example of a thin-air value,
LB+data+data, augments the basic load-buffering program by adding data-dependencies
from the writes to the reads in each thread: