The C11 and C++11 Concurrency Model

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ItisnotyetobviousthatthewritesofThread1mustbepropagatedtoThread3before
the write of Thread 2, however. A new guarantee called B-cumulativity, provides ordering
through executions with chained dependencies following an lwsync. In this example, B-
cumulativity ensures that the store of x is propagated to Thread 3 before the store of
z.
The example above shows that B-cumulativity extends ordering to the right of an
lwsync, A-cumulativity extends ordering to the left: consider the following example,
called WRC+lwsync+addr for write-to-read causality [37] with an lwsync and an address
dependency. Thread 1 writes x, and Thread 2 writes y:
int x = 0;
int y = 0;
x = 1; r1 = x; r2 = y;
lwsync r3 = *(&x + r2 - r2);
y = 1;
The lwsync and the address dependency prevent thread-local speculation from occurring
on Threads 2 and 3, but there is so far nothing to force the write on Thread 1
to propagate to Thread 3 before the write of Thread 2, allowing the outcome 1/1/0 for
the reads of x on Thread 2, y on Thread 3 and x on Thread 3. We define the group A
writes to be those that have propagated to the thread of an lwsync at the point that
it is executed. The write of x is in the group A of the lwsync in the execution of the
program above. A-cumulativity requires group A writes to propagate to all threads before
writes that follow the barrier in program order, guaranteeing that the outcome 1/1/0 is
forbidden on Power and ARM architectures; it provides ordering to dependency chains to
the left of an lwsync.
Note that in either case of cumulativity, if the dependencies were replaced by lwsyncs
or syncs, then the ordering would still be guaranteed.
Load-linked store-conditional ThePowerandARMarchitecturesprovideload-linked
(LL) and store-conditional (SC) instructions that allow the programmer to load from a
location, and then store only if no other thread accessed the location in the interval
between the two. These instructions allow the programmer to establish consensus as the
global lock did in x86. The load-linked instruction is a load from memory that works in
conjunction with a program-order-later store-conditional. The store-conditional has two
possible outcomes; it can store to memory, or it may fail if the coherence commitment
order is sufficiently unconstrained, allowing future steps of the abstract machine to place
writes before it. On success, load-linked and store-conditional instructions atomically
read and then write a location, and can be used to implement language features like
compare-and-swap.