- Page 1: The C11 and C++11 Concurrency Model
- Page 5: Mark John Batty The C11 and C++11 C
- Page 8 and 9: 8 3.5.1 Release sequences . . . . .
- Page 10 and 11: 10 B.1 The pre-execution type . . .
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- Page 14 and 15: 14 stores to memory are interleaved
- Page 16 and 17: 16 still, relaxed-concurrencybugsca
- Page 18 and 19: 18 to sequential consistency [37],
- Page 20 and 21: 20 ory model. It has been used for
- Page 22 and 23: 22 by Dubois et al. [48]. C/C++11 c
- Page 24 and 25: 24 There has been some work on veri
- Page 26 and 27: 26 int x = 0; int y = 0; x = 1; y =
- Page 28 and 29: 28 On the SC memory model this prog
- Page 30 and 31: 30 The x86 architecture provides th
- Page 32 and 33: 32 Write request Read request Barri
- Page 34 and 35: 34 coherence-commitment order restr
- Page 36 and 37: 36 Multi-copy atomicity Some memory
- Page 38 and 39: 38 Further details of the Power and
- Page 40 and 41: 40 they can be guaranteed with no d
- Page 42 and 43: 42 indivisible events that affect t
- Page 44 and 45: 44 undefined behaviour. In the prog
- Page 46 and 47: 46 On each architecture, this is su
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- Page 52 and 53: 52 int main() { int x = 2; int y =
- Page 54 and 55: 54 a:W NA x=0 sb int main() { int x
- Page 56 and 57: 56 effects of a particular read are
- Page 58 and 59: 58 | Blocked rmw l → lk l = Atomi
- Page 60 and 61: 60 let det read (Xo, Xw, :: (“vse
- Page 62 and 63: 62 let indeterminate reads (Xo, Xw,
- Page 64 and 65: 64 let single thread memory model =
- Page 66 and 67: 66 becomes: int main() { int x = 0;
- Page 68 and 69: 68 additional-synchronises-withedge
- Page 70 and 71: 70 let locks only consistent locks
- Page 72 and 73: 72 let data races (Xo, Xw, (“hb
- Page 74 and 75: 74 = ( (¬ (a = b)) ∧ is write a
- Page 76 and 77: 76 the atomic location is accessed.
- Page 78 and 79: 78 Message passing, MP The first ex
- Page 80 and 81: 80 a:W NA x=0 sb rf b:W NA y=0 rf r
- Page 82 and 83: 82 the C/C++11 analogue of the test
- Page 84 and 85: 84 On Power and ARM, the analogue o
- Page 86 and 87: 86 stores of this fragment of the l
- Page 88 and 89: 88 int main() { atomic_int x = 0; a
- Page 90 and 91: 90 int main() { int x = 0; atomic_i
- Page 92 and 93: 92 and ARM all guarantee that each
- Page 94 and 95: 94 Release fences In the example in
- Page 96 and 97: 96 ( is fence a ∧ is release a
- Page 98 and 99: 98 3.7 Programs with SC atomics Pro
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100 not forbid the store-buffering
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102 int main() { atomic_int x = 0;
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104 ( (w, w ′ ) ∈ Xw.mo ∧ (w
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106 int main() { atomic_int x = 0;
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108 conjunct of sc fenced sc fences
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110 int main() { int x = 0; atomic_
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112 let r = sw ∪ dob ∪ (compose
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114 of the read. This write forms t
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116
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118 behaviour of the memory model.
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120 At the top right, there are con
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122 int main() { atomic_int x = 0;
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124 A release sequence headed by a
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126 [ Note: The visible sequence of
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128 int main() { atomic_int x = 0;
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130 5.6 Undefined loops In C/C++11
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132 Next consider the execution bel
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134 ultimately faulty specification
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136 air problem. It seems clear the
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138 void main() { atomic_int x = 0;
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140 5.10.2 Possible solutions One c
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142 programs with thin-air values w
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144 Java introduces a great deal of
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146 int main() { atomic_int x = 2;
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148
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150 standard model T. 1 with consum
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152 tions, or they both produce und
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154 the two models are almost ident
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156 h, in the acyclic relation mo.
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158 | RMW mo → (mo ∈ {Acq rel,
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160 Programs without SC atomics Rem
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162 match a with | Lock → true |
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164 Theorem 8. (∀ opsem p. static
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166 is release rel ∧ ( (b = rel)
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168 Now we show that this equivalen
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170 is a dynamic property that can
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172 standard model T. 1 with consum
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174 [...][ Note: It can be shown th
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176 • consistent hb Furthermore,
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178 | Load mo → (mo ∈ {NA, Seq
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180 The induction will proceed by a
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182 exists a consistent execution i
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184 The domain and range of hbscr i
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186 implies that there is no tot in
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188 There are two directions to est
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190 incorporates the new action. Th
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192 Now for each sort of fault, we
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194 Theorem 14. For a program that
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196 we need only show that the sc-o
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198
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200 This chapter presents theorems
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202 C++0x actions a:W NA x=1 d:R AC
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204 and consume atomics require the
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206 Thread 0 has an lwsync as in th
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208 The thread and storage subsyste
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210 we know that any inter-thread h
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212
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214 behaviour in the specification.
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216 atomic Seq S; void init() { sto
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218 Message passing (MP): int a, b,
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220 in composition with a client wi
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222 tation in an arbitrary client c
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224 push and pop in an execution. T
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226 execution of the component exte
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228 Then for some Z ∈ C(L 2 )(I
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230
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232 it is possible to identify erra
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234 The release-sequence of C/C++11
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236 mer’s memory model. The CPU a
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238 17.3 defines additional terms t
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240 and the other is not, or if the
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242 abstract machine with the same
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244 a = ((a + b) + 32765); since if
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246 | RMW of aid ∗ tid ∗ memory
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248 not otherwise specifically sequ
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250 gram can potentially access eve
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252 acquire fence, a release fence,
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254 This relation does not order th
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256 performs a consume operation on
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258 • A is sequenced before B, or
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260 The model represents visible si
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262 where the three relations disag
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264 CoRW In this coherence violatio
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266 referred to as “sequential co
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268 29 Atomic operations library [a
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270 In the model, the memory order
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272 [...]) (∃c∈actions. (a, c)
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274 4 For an atomic operation B tha
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276 ForatomicoperationsAandB onanat
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278 However, implementations should
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280 | RMW l → lk l = Atomic | Fen
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282 The model captures these potent
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284 bool atomic_compare_exchange_we
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286 expected = current.load(); do {
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288 31 Effects: fetch key(operand)
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290 [...] (a, x) ∈ sb ∧ (x, y)
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292 extern "C" void atomic_signal_f
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294 30.3.1.2 thread constructors [t
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296 Header synopsis [elided] 30.4.
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298 The behaviour of locks and unlo
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300 9 Postcondition: The calling th
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302 let locks only bad mutexes (Xo,
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304 after the unlock call returns.
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306 |〉 threads : set (tid); lk :
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308 let aid of a = match a with | L
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310 Effects: Blocks the calling thr
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312 atomic location. On failure the
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314 Requires: The failure argument
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316 | Fence mo → mo ∈ {Release,
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318
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320 The thread-local semantics coll
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322 B.2.2 Modification order Modifi
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324 isIrreflexive Xw.lo ∧ ∀ a
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326 A release sequence headed by a
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328 creation, mutex accesses, atomi
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330
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332 An atomic operation A that is a
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334 B.3.5 Dependency ordered before
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336 the inter-thread-happens-before
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338 B.3.9 Visible sequence of side
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340 B.4.1 Coherence The previous se
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342 The coherence restriction These
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344 Second read-from derivative In
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346 To cover the second and third c
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348 This restriction requires reads
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350 [...]If a side effect on a scal
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352 The model captures these potent
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354 successful to have an interveni
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356 each empty M.undefined X then D
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358 type program impl = nat type ti
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360 let named predicate tree measur
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362 C.3 Projection functions let ai
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364 | RMW → true | → false end
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366 | Store mo → mo = Seq cst | R
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368 blocking observed Xo.actions Xo
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370 a ′ ∈ fringe set Xo ′ A
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372 val indeterminate reads : candi
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374 let locks only consistent locks
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376 val locks only behaviour : ∀
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378 |〉 〈| rf flag = true; mo fl
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380 (“release acquire coherent me
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382 val release acquire relaxed beh
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384 behaviourrelease acquire fenced
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386 ∀ (Xo, Xw, rl) ∈ Xs. ∀ a
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388 let sc fenced behaviour opsem (
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390 behaviour with consume memory m
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392 let release acquire SC conditio
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394 let bounded executions (Xs : se
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396 { (a, b) | ∀ a ∈ Xo.actions
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398 statically satisfied single thr
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400 let vse = visible side effect s
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402
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404 [15] J. Alglave, D. Kroening, V
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406 [42] L. Censier and P. Feautrie
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408 [68] S. Mador-Haim, L. Maranget
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410 ization and analysis of message
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Index actions, 41, 245 additional s
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414 Last updated: Saturday 29 th No