The C11 and C++11 Concurrency Model

90
int main() {
int x = 0; atomic_int y = 0;
{{{ { x = 1;
y.store(1,release); }
||| { while (y.load(acquire) == 1);
r1 = x; }
}}}
return 0;
}
c:W NA x=1
rf
e:R ACQ y=1
sb sb
rf,sw
d:W REL y=1 f:R NA x=1
On the Power architecture, the compilation mapping places an lwsync barrier above
the write to the atomic location. It is the fact that the barrier occurs between the nonatomic
write and the atomic write that preserves the ordering on the hardware. Inserting
a relaxed write to the same location after the release write gives us the following program
(the rs edge will be explained below):
int main() {
int x = 0; atomic_int y = 0;
{{{ { x = 1;
y.store(1,release);
y.store(1,relaxed); }
||| { r1 = y.load(acquire);
r2 = x; }
}}}
return 0;
}
c:W NA x=1rf
f:R ACQ y=1
sb sb
d:W REL y=1 g:R NA x=1
sb,rs rf
e:W RLX y=1
The default Power compilation of the two child threads is given below:
stw 1,0(x) lwz r1,0(y)
lwsync cmpw r1,r1
stw 1,0(y) beq LC00
stw 1,0(y) LC00:
isync
lwz r2,0(x)
There is an lwsync barrier above the first write to the atomic location. The lwsync
barrier forces the write to x to be committed and propagated to the other thread before
program-order-later writes, and therefore does not just order the first write to the atomic
location; it serves to order the second write to the atomic location as well. The lwsync
prevents the out-of-order commitment or propagation of the write of x and either write of
y. Thebranch-control-isynconthesecondthreadinhibitsreadspeculation. Consequently,
it is not possible to see MP relaxed behaviour in the program above. Both ARM and