The C11 and C++11 Concurrency Model

31
Executions of this program might read from y any number of times before seeing the
value 1, or they may never see the value 1. We focus on executions where the first read
of y reads the value 1, so we simplify the test to remove the loop:
int x = 0;
int y = 0;
x = 1; r1 = y;
y = 1; r2 = x;
In the sequentially consistent memory model, the behaviour of the program is given
by the set of all interleavings of the memory accesses, as presented in the table below:
Interleaving
Outcome
x = 0; y = 0; x = 1; y = 1; r1 = y; r2 = x r1 = 1, r2 = 1
x = 0; y = 0; x = 1; r1 = y; y = 1; r2 = x
x = 0; y = 0; r1 = y; x = 1; y = 1; r2 = x
r1 = 0, r2 = 1
x = 0; y = 0; x = 1; r1 = y; r2 = x; y = 1
x = 0; y = 0; r1 = y; x = 1; r2 = x; y = 1
x = 0; y = 0; r1 = y; r2 = x; x = 1; y = 1 r1 = 0, r2 = 0
Note that the outcome 1/0 is not allowed under sequential consistency or x86 — the
first-in-first-out nature of the write buffers makes it impossible to see the second write
without the first already having flushed to memory. On Power, the relaxed behaviour
could be introduced by any of the following three architectural optimisations:
• Thelefthandthread’swritesmightbecommittedtomemoryoutoforder, byreordering
the stores.
• The right hand thread’s reads might be performed out of order by some speculation
mechanism.
• The memory subsystem might propagate the writes to the other thread out-of-order.
The Power and ARM architectures expose all three sorts of reordering mentioned
above, and produce the result 1/0 on the message-passing example.
The Power and ARM abstract machine Sarkar et al. define the Power and ARM
architecturememorymodel asan abstractmachine. This machineissplit between threadlocal
details such as speculation, and memory-subsystem details such as write propagation.
Threads can make write, read and barrier requests, and the memory subsystem
can respond with barrier acknowledgements and read responses. Read requests, rather
than containing a simple value, are associated with a particular write that is identified
by a read-response event. Each read-request from a thread results in an immediate readresponse
from the storage subsystem.