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# tidu271

## Theory of Operation

Theory of Operation www.ti.com C CM (±ΔC) mismatch causes asymmetric e n attenuation, resulting in significant differential noise, which is also amplified by PGA gain along with sensor input. Figure 18. Common Mode Filter (Undesired) C CM (±ΔC) mismatch causes asymmetric e n attenuation. As long as CDIFF ≥ 10 CCM, differential noise is attentuated to an insignificant level. Figure 19. Common Mode and Differential Mode Filter (Desired) F F F DM DM DM 1 C68 C61 2R47 R45C65 C68 C61 1 0.1 µF 0.1 µF 2499 499 1 µF 0.1 µF 0.1 µF 152 Hz (5) 18 Temperature Sensor Interface Module for Programmable Logic Controllers TIDU271–May 2014 (PLC) Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated

www.ti.com F F CM _ 1 CM _ 2 1 2 RS1 C 1 CM1 2 RS2 CCM2 Theory of Operation (6) F F CM _ 1 CM _ 2 3.2 KHz (7) 5.1.6 PGA Gain and Common Mode Voltage The K-Type thermocouple has a temperature range of –270°C to 1372°C. The K-Type thermocouple produces a voltage input to the PGA ranges from –6.458 mV to 54.886 mV. Therefore, the thermocouple full scale input range (V TC_IN_FS ) is as shown in and Equation 9. V TC_IN_FS = [54.886 mV – (–6.458mV) ] = 61.344 mV (8) VREF 2.048 V PGA Gain 33.4 V / V VIN_FS 61.344 mV (9) The closest PGA gain supported by ADS1220 is 32 V/V. The differential full scale input voltage (V FS ) range for the PGA at a gain of 32 V/V is ±64 mV. The thermocouple full scale input voltage (V TC_IN_FS ) lies within the PGA full scale input. K-type thermocouple temperature range: K-type thermocouple voltage output overlapped on PGA full scale input range: PGA output overlapped on ADC full scale input range: The ADC can measure inputs differentially, which means the ADC measures one input with respect to another input with both inputs' active signals. For 5-V single power supply operation, AIN_P and AIN_N signals should not be allowed to swing below ground. Therefore, it is important to set common mode voltage of the differential signals equal to the mid-supply so that the differential signals swing above and below the common mode voltage and always remain within the valid ADC range as shown below in Figure 20. A1 and A2 are not rail-to-rail output amplifiers. Therefore ADC_IN_P and ADC_IN_N have to be within (AVSS + 0.2 V) and (AVDD – 0.2 V). Equation 10 shows the most confusing common mode voltage requirement for the inputs: VIN PGA VIN PGA CM AVSS 0.2 V V AVDD 0.2 V 2 2 For example, AVDD = 5 V, AVSS = 0 V, PGA Gain = 32 V/V and Internal ADC Reference (V REF ) = 2.048 V. Therefore, the maximum possible differential input voltage that can be applied is VREF 2.048 V 0.064 V PGA Gain 32 V/V So, the allowed common mode voltage range is 1.224 V ≤ V CM ≤ 3.776 V. (10) TIDU271–May 2014 Submit Documentation Feedback Temperature Sensor Interface Module for Programmable Logic Controllers (PLC) Copyright © 2014, Texas Instruments Incorporated 19